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| author | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2013-07-27 22:11:24 +0000 |
|---|---|---|
| committer | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2013-07-27 22:11:24 +0000 |
| commit | ce6a36c7f7c88e7ca0fda816f9282237bb86829d (patch) | |
| tree | 611bf9beb2281d34260ca87fc189a0ddc864819a /libdde-linux26/libdde_linux26/contrib/include/linux/cache.h | |
| parent | bb9d6cd642f9189b8102d566c8c46a6de1d2c5f7 (diff) | |
| parent | 4fbe7358c7747a9165f776eb19addbb9baf7def2 (diff) | |
Merge branch 'upstream-merged'
Diffstat (limited to 'libdde-linux26/libdde_linux26/contrib/include/linux/cache.h')
| -rw-r--r-- | libdde-linux26/libdde_linux26/contrib/include/linux/cache.h | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/libdde-linux26/libdde_linux26/contrib/include/linux/cache.h b/libdde-linux26/libdde_linux26/contrib/include/linux/cache.h new file mode 100644 index 00000000..97e24881 --- /dev/null +++ b/libdde-linux26/libdde_linux26/contrib/include/linux/cache.h @@ -0,0 +1,67 @@ +#ifndef __LINUX_CACHE_H +#define __LINUX_CACHE_H + +#include <linux/kernel.h> +#include <asm/cache.h> + +#ifndef L1_CACHE_ALIGN +#define L1_CACHE_ALIGN(x) ALIGN(x, L1_CACHE_BYTES) +#endif + +#ifndef SMP_CACHE_BYTES +#define SMP_CACHE_BYTES L1_CACHE_BYTES +#endif + +#ifndef __read_mostly +#define __read_mostly +#endif + +#ifndef ____cacheline_aligned +#define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES))) +#endif + +#ifndef ____cacheline_aligned_in_smp +#ifdef CONFIG_SMP +#define ____cacheline_aligned_in_smp ____cacheline_aligned +#else +#define ____cacheline_aligned_in_smp +#endif /* CONFIG_SMP */ +#endif + +#ifndef __cacheline_aligned +#define __cacheline_aligned \ + __attribute__((__aligned__(SMP_CACHE_BYTES), \ + __section__(".data.cacheline_aligned"))) +#endif /* __cacheline_aligned */ + +#ifndef __cacheline_aligned_in_smp +#ifdef CONFIG_SMP +#define __cacheline_aligned_in_smp __cacheline_aligned +#else +#define __cacheline_aligned_in_smp +#endif /* CONFIG_SMP */ +#endif + +/* + * The maximum alignment needed for some critical structures + * These could be inter-node cacheline sizes/L3 cacheline + * size etc. Define this in asm/cache.h for your arch + */ +#ifndef INTERNODE_CACHE_SHIFT +#define INTERNODE_CACHE_SHIFT L1_CACHE_SHIFT +#endif + +#if !defined(____cacheline_internodealigned_in_smp) +#if defined(CONFIG_SMP) +#define ____cacheline_internodealigned_in_smp \ + __attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT)))) +#else +#define ____cacheline_internodealigned_in_smp +#endif +#endif + +#ifndef CONFIG_ARCH_HAS_CACHE_LINE_SIZE +#define cache_line_size() L1_CACHE_BYTES +#endif + +#endif /* __LINUX_CACHE_H */ |
