Bug Summary

File:obj-scan-build/../linux/src/drivers/block/triton.c
Location:line 112, column 18
Description:Value stored to 'rq' during its initialization is never read

Annotated Source Code

1/*
2 * linux/drivers/block/triton.c Version 1.13 Aug 12, 1996
3 * Version 1.13a June 1998 - new chipsets
4 * Version 1.13b July 1998 - DMA blacklist
5 * Version 1.14 June 22, 1999
6 *
7 * Copyright (c) 1998-1999 Andre Hedrick
8 * Copyright (c) 1995-1996 Mark Lord
9 * May be copied or modified under the terms of the GNU General Public License
10 */
11
12/*
13 * This module provides support for Bus Master IDE DMA functions in various
14 * motherboard chipsets and PCI controller cards.
15 * Please check /Documentation/ide.txt and /Documentation/udma.txt for details.
16 */
17
18#include <linux/config.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/timer.h>
22#include <linux/mm.h>
23#include <linux/ioport.h>
24#include <linux/interrupt.h>
25#include <linux/blkdev.h>
26#include <linux/hdreg.h>
27#include <linux/pci.h>
28#include <linux/bios32.h>
29
30#include <asm/io.h>
31#include <asm/dma.h>
32#include <asm/irq.h>
33
34#include "ide.h"
35
36#undef DISPLAY_TRITON_TIMINGS /* define this to display timings */
37#undef DISPLAY_APOLLO_TIMINGS /* define this for extensive debugging information */
38#undef DISPLAY_ALI15X3_TIMINGS /* define this for extensive debugging information */
39
40#if defined(CONFIG_PROC_FS1)
41#include <linux/stat.h>
42#include <linux/proc_fs.h>
43#ifdef DISPLAY_APOLLO_TIMINGS
44#include <linux/via_ide_dma.h>
45#endif
46#ifdef DISPLAY_ALI15X3_TIMINGS
47#include <linux/ali_ide_dma.h>
48#endif
49#endif
50
51/*
52 * good_dma_drives() lists the model names (from "hdparm -i")
53 * of drives which do not support mword2 DMA but which are
54 * known to work fine with this interface under Linux.
55 */
56const char *good_dma_drives[] = {"Micropolis 2112A",
57 "CONNER CTMA 4000",
58 "CONNER CTT8000-A",
59 "QEMU HARDDISK",
60 NULL((void *) 0)};
61
62/*
63 * bad_dma_drives() lists the model names (from "hdparm -i")
64 * of drives which supposedly support (U)DMA but which are
65 * known to corrupt data with this interface under Linux.
66 *
67 * Note: the list was generated by statistical analysis of problem
68 * reports. It's not clear if there are problems with the drives,
69 * or with some combination of drive/controller or what.
70 *
71 * You can forcibly override this if you wish. This is the kernel
72 * 'Tread carefully' list.
73 *
74 * Finally see http://www.wdc.com/quality/err-rec.html if you have
75 * one of the listed drives.
76 */
77const char *bad_dma_drives[] = {"WDC AC11000H",
78 "WDC AC22100H",
79 "WDC AC32500H",
80 "WDC AC33100H",
81 NULL((void *) 0)};
82
83/*
84 * Our Physical Region Descriptor (PRD) table should be large enough
85 * to handle the biggest I/O request we are likely to see. Since requests
86 * can have no more than 256 sectors, and since the typical blocksize is
87 * two sectors, we could get by with a limit of 128 entries here for the
88 * usual worst case. Most requests seem to include some contiguous blocks,
89 * further reducing the number of table entries required.
90 *
91 * The driver reverts to PIO mode for individual requests that exceed
92 * this limit (possible with 512 byte blocksizes, eg. MSDOS f/s), so handling
93 * 100% of all crazy scenarios here is not necessary.
94 *
95 * As it turns out though, we must allocate a full 4KB page for this,
96 * so the two PRD tables (ide0 & ide1) will each get half of that,
97 * allowing each to have about 256 entries (8 bytes each) from this.
98 */
99#define PRD_BYTES8 8
100#define PRD_ENTRIES((1 << 12) / (2 * 8)) (PAGE_SIZE(1 << 12) / (2 * PRD_BYTES8))
101#define DEFAULT_BMIBA0xe800 0xe800 /* in case BIOS did not init it */
102#define DEFAULT_BMCRBA0xcc00 0xcc00 /* VIA's default value */
103#define DEFAULT_BMALIBA0xd400 0xd400 /* ALI's default value */
104
105/*
106 * dma_intr() is the handler for disk read/write DMA interrupts
107 */
108static void dma_intr (ide_drive_t *drive)
109{
110 byte stat, dma_stat;
111 int i;
112 struct request *rq = HWGROUP(drive)((ide_hwgroup_t *)(((ide_hwif_t *)((drive)->hwif))->hwgroup
))->rq;
Value stored to 'rq' during its initialization is never read
113 unsigned short dma_base = HWIF(drive)((ide_hwif_t *)((drive)->hwif))->dma_base;
114
115 dma_stat = inb(dma_base+2)((__builtin_constant_p((dma_base+2)) && (dma_base+2) <
256) ? __inbc(dma_base+2) : __inb(dma_base+2)); /* get DMA status */
116 outb(inb(dma_base)&~1, dma_base)((__builtin_constant_p((dma_base)) && (dma_base) <
256) ? __outbc((((__builtin_constant_p((dma_base)) &&
(dma_base) < 256) ? __inbc(dma_base) : __inb(dma_base))&
~1),(dma_base)) : __outb((((__builtin_constant_p((dma_base)) &&
(dma_base) < 256) ? __inbc(dma_base) : __inb(dma_base))&
~1),(dma_base))); /* stop DMA operation */
117 stat = GET_STAT()(byte)((__builtin_constant_p(((((ide_hwif_t *)((drive)->hwif
))->io_base+(7)))) && ((((ide_hwif_t *)((drive)->
hwif))->io_base+(7))) < 256) ? __inbc_p((((ide_hwif_t *
)((drive)->hwif))->io_base+(7))) : __inb_p((((ide_hwif_t
*)((drive)->hwif))->io_base+(7)))); /* get drive status */
118 if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)(((stat)&(((0x40 | 0x10))|(drive->bad_wstat|0x08)))==(
(0x40 | 0x10)))) {
119 if ((dma_stat & 7) == 4) { /* verify good DMA status */
120 rq = HWGROUP(drive)((ide_hwgroup_t *)(((ide_hwif_t *)((drive)->hwif))->hwgroup
))->rq;
121 for (i = rq->nr_sectors; i > 0;) {
122 i -= rq->current_nr_sectors;
123 ide_end_request(1, HWGROUP(drive)((ide_hwgroup_t *)(((ide_hwif_t *)((drive)->hwif))->hwgroup
)));
124 }
125 return;
126 }
127 printk("%s: bad DMA status: 0x%02x\n", drive->name, dma_stat);
128 }
129 sti()__asm__ __volatile__ ("sti": : :"memory");
130 ide_error(drive, "dma_intr", stat);
131}
132
133/*
134 * build_dmatable() prepares a dma request.
135 * Returns 0 if all went okay, returns 1 otherwise.
136 */
137static int build_dmatable (ide_drive_t *drive)
138{
139 struct request *rq = HWGROUP(drive)((ide_hwgroup_t *)(((ide_hwif_t *)((drive)->hwif))->hwgroup
))->rq;
140 struct buffer_head *bh = rq->bh;
141 unsigned long size, addr, *table = HWIF(drive)((ide_hwif_t *)((drive)->hwif))->dmatable;
142 unsigned int count = 0;
143
144 do {
145 /*
146 * Determine addr and size of next buffer area. We assume that
147 * individual virtual buffers are always composed linearly in
148 * physical memory. For example, we assume that any 8kB buffer
149 * is always composed of two adjacent physical 4kB pages rather
150 * than two possibly non-adjacent physical 4kB pages.
151 */
152 if (bh == NULL((void *) 0)) { /* paging and tape requests have (rq->bh == NULL) */
153 addr = virt_to_busvirt_to_phys (rq->buffer);
154#ifdef CONFIG_BLK_DEV_IDETAPE
155 if (drive->media == ide_tape)
156 size = drive->tape.pc->request_transfer;
157 else
158#endif /* CONFIG_BLK_DEV_IDETAPE */
159 size = rq->nr_sectors << 9;
160 } else {
161 /* group sequential buffers into one large buffer */
162 addr = virt_to_busvirt_to_phys (bh->b_data);
163 size = bh->b_size;
164 while ((bh = bh->b_reqnext) != NULL((void *) 0)) {
165 if ((addr + size) != virt_to_busvirt_to_phys (bh->b_data))
166 break;
167 size += bh->b_size;
168 }
169 }
170
171 /*
172 * Fill in the dma table, without crossing any 64kB boundaries.
173 * We assume 16-bit alignment of all blocks.
174 */
175 while (size) {
176 if (++count >= PRD_ENTRIES((1 << 12) / (2 * 8))) {
177 printk("%s: DMA table too small\n", drive->name);
178 return 1; /* revert to PIO for this request */
179 } else {
180 unsigned long bcount = 0x10000 - (addr & 0xffff);
181 if (bcount > size)
182 bcount = size;
183 *table++ = addr;
184 *table++ = bcount & 0xffff;
185 addr += bcount;
186 size -= bcount;
187 }
188 }
189 } while (bh != NULL((void *) 0));
190 if (count) {
191 *--table |= 0x80000000; /* set End-Of-Table (EOT) bit */
192 return 0;
193 }
194 printk("%s: empty DMA table?\n", drive->name);
195 return 1; /* let the PIO routines handle this weirdness */
196}
197
198/*
199 * We will only enable drives with multi-word (mode2) (U)DMA capabilities,
200 * and ignore the very rare cases of drives that can only do single-word
201 * (modes 0 & 1) (U)DMA transfers. We also discard "blacklisted" hard disks.
202 */
203static int config_drive_for_dma (ide_drive_t *drive)
204{
205#ifndef CONFIG_BLK_DEV_FORCE_DMA
206 const char **list;
207 struct hd_driveid *id = drive->id;
208#endif
209
210#ifdef CONFIG_BLK_DEV_FORCE_DMA
211 drive->using_dma = 1;
212 return 0;
213#else
214 if (HWIF(drive)((ide_hwif_t *)((drive)->hwif))->chipset == ide_hpt343) {
215 drive->using_dma = 0; /* no DMA */
216 return 1; /* DMA disabled */
217 }
218
219 if (id && (id->capability & 1)) {
220 /* Consult the list of known "bad" drives */
221 list = bad_dma_drives;
222 while (*list) {
223 if (!strcmp(*list++,id->model)) {
224 drive->using_dma = 0; /* no DMA */
225 printk("ide: Disabling DMA modes on %s drive (%s).\n", drive->name, id->model);
226 return 1; /* DMA disabled */
227 }
228 }
229 /* Enable DMA on any drive that has mode 4 or 2 UltraDMA enabled */
230 if (id->field_valid & 4) { /* UltraDMA */
231 /* Enable DMA on any drive that has mode 4 UltraDMA enabled */
232 if (((id->dma_ultra & 0x1010) == 0x1010) &&
233 (id->word93 & 0x2000) &&
234 (HWIF(drive)((ide_hwif_t *)((drive)->hwif))->chipset == ide_ultra66)) {
235 drive->using_dma = 1;
236 return 0; /* DMA enabled */
237 } else
238 /* Enable DMA on any drive that has mode 2 UltraDMA enabled */
239 if ((id->dma_ultra & 0x404) == 0x404) {
240 drive->using_dma = 1;
241 return 0; /* DMA enabled */
242 }
243 }
244 /* Enable DMA on any drive that has mode2 DMA enabled */
245 if (id->field_valid & 2) /* regular DMA */
246 if ((id->dma_mword & 0x404) == 0x404) {
247 drive->using_dma = 1;
248 return 0; /* DMA enabled */
249 }
250 /* Consult the list of known "good" drives */
251 list = good_dma_drives;
252 while (*list) {
253 if (!strcmp(*list++,id->model)) {
254 drive->using_dma = 1;
255 return 0; /* DMA enabled */
256 }
257 }
258 }
259 return 1; /* DMA not enabled */
260#endif
261}
262
263/*
264 * triton_dmaproc() initiates/aborts DMA read/write operations on a drive.
265 *
266 * The caller is assumed to have selected the drive and programmed the drive's
267 * sector address using CHS or LBA. All that remains is to prepare for DMA
268 * and then issue the actual read/write DMA/PIO command to the drive.
269 *
270 * For ATAPI devices, we just prepare for DMA and return. The caller should
271 * then issue the packet command to the drive and call us again with
272 * ide_dma_begin afterwards.
273 *
274 * Returns 0 if all went well.
275 * Returns 1 if DMA read/write could not be started, in which case
276 * the caller should revert to PIO for the current request.
277 */
278static int triton_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
279{
280 unsigned long dma_base = HWIF(drive)((ide_hwif_t *)((drive)->hwif))->dma_base;
281 unsigned int reading = (1 << 3);
282
283 switch (func) {
284 case ide_dma_abort:
285 outb(inb(dma_base)&~1, dma_base)((__builtin_constant_p((dma_base)) && (dma_base) <
256) ? __outbc((((__builtin_constant_p((dma_base)) &&
(dma_base) < 256) ? __inbc(dma_base) : __inb(dma_base))&
~1),(dma_base)) : __outb((((__builtin_constant_p((dma_base)) &&
(dma_base) < 256) ? __inbc(dma_base) : __inb(dma_base))&
~1),(dma_base))); /* stop DMA */
286 return 0;
287 case ide_dma_check:
288 return config_drive_for_dma (drive);
289 case ide_dma_write:
290 reading = 0;
291 case ide_dma_read:
292 break;
293 case ide_dma_status_bad:
294 return ((inb(dma_base+2)((__builtin_constant_p((dma_base+2)) && (dma_base+2) <
256) ? __inbc(dma_base+2) : __inb(dma_base+2)) & 7) != 4); /* verify good DMA status */
295 case ide_dma_transferred:
296#if 0
297 return (number of bytes actually transferred);
298#else
299 return (0);
300#endif
301 case ide_dma_begin:
302 outb(inb(dma_base)|1, dma_base)((__builtin_constant_p((dma_base)) && (dma_base) <
256) ? __outbc((((__builtin_constant_p((dma_base)) &&
(dma_base) < 256) ? __inbc(dma_base) : __inb(dma_base))|1
),(dma_base)) : __outb((((__builtin_constant_p((dma_base)) &&
(dma_base) < 256) ? __inbc(dma_base) : __inb(dma_base))|1
),(dma_base))); /* begin DMA */
303 return 0;
304 default:
305 printk("triton_dmaproc: unsupported func: %d\n", func);
306 return 1;
307 }
308 if (build_dmatable (drive))
309 return 1;
310 outl(virt_to_bus (HWIF(drive)->dmatable), dma_base + 4)((__builtin_constant_p((dma_base + 4)) && (dma_base +
4) < 256) ? __outlc((virt_to_phys (((ide_hwif_t *)((drive
)->hwif))->dmatable)),(dma_base + 4)) : __outl((virt_to_phys
(((ide_hwif_t *)((drive)->hwif))->dmatable)),(dma_base
+ 4))); /* PRD table */
311 outb(reading, dma_base)((__builtin_constant_p((dma_base)) && (dma_base) <
256) ? __outbc((reading),(dma_base)) : __outb((reading),(dma_base
))); /* specify r/w */
312 outb(inb(dma_base+2)|0x06, dma_base+2)((__builtin_constant_p((dma_base+2)) && (dma_base+2) <
256) ? __outbc((((__builtin_constant_p((dma_base+2)) &&
(dma_base+2) < 256) ? __inbc(dma_base+2) : __inb(dma_base
+2))|0x06),(dma_base+2)) : __outb((((__builtin_constant_p((dma_base
+2)) && (dma_base+2) < 256) ? __inbc(dma_base+2) :
__inb(dma_base+2))|0x06),(dma_base+2))); /* clear status bits */
313#ifdef CONFIG_BLK_DEV_IDEATAPI1
314 if (drive->media != ide_disk)
315 return 0;
316#endif /* CONFIG_BLK_DEV_IDEATAPI */
317 ide_set_handler(drive, &dma_intr, WAIT_CMD(10*100)); /* issue cmd to drive */
318 OUT_BYTE(reading ? WIN_READDMA : WIN_WRITEDMA, IDE_COMMAND_REG)((__builtin_constant_p((((((ide_hwif_t *)((drive)->hwif))->
io_base+(7))))) && (((((ide_hwif_t *)((drive)->hwif
))->io_base+(7)))) < 256) ? __outbc_p(((reading ? 0xc8 :
0xca)),(((((ide_hwif_t *)((drive)->hwif))->io_base+(7)
)))) : __outb_p(((reading ? 0xc8 : 0xca)),(((((ide_hwif_t *)(
(drive)->hwif))->io_base+(7))))));
319 outb(inb(dma_base)|1, dma_base)((__builtin_constant_p((dma_base)) && (dma_base) <
256) ? __outbc((((__builtin_constant_p((dma_base)) &&
(dma_base) < 256) ? __inbc(dma_base) : __inb(dma_base))|1
),(dma_base)) : __outb((((__builtin_constant_p((dma_base)) &&
(dma_base) < 256) ? __inbc(dma_base) : __inb(dma_base))|1
),(dma_base))); /* begin DMA */
320 return 0;
321}
322
323#ifdef DISPLAY_TRITON_TIMINGS
324/*
325 * print_triton_drive_flags() displays the currently programmed options
326 * in the i82371 (Triton) for a given drive.
327 *
328 * If fastDMA is "no", then slow ISA timings are used for DMA data xfers.
329 * If fastPIO is "no", then slow ISA timings are used for PIO data xfers.
330 * If IORDY is "no", then IORDY is assumed to always be asserted.
331 * If PreFetch is "no", then data pre-fetch/post are not used.
332 *
333 * When "fastPIO" and/or "fastDMA" are "yes", then faster PCI timings and
334 * back-to-back 16-bit data transfers are enabled, using the sample_CLKs
335 * and recovery_CLKs (PCI clock cycles) timing parameters for that interface.
336 */
337static void print_triton_drive_flags (unsigned int unit, byte flags)
338{
339 printk(" %s ", unit ? "slave :" : "master:");
340 printk( "fastDMA=%s", (flags&9) ? "on " : "off");
341 printk(" PreFetch=%s", (flags&4) ? "on " : "off");
342 printk(" IORDY=%s", (flags&2) ? "on " : "off");
343 printk(" fastPIO=%s\n", ((flags&9)==1) ? "on " : "off");
344}
345#endif /* DISPLAY_TRITON_TIMINGS */
346
347static void init_triton_dma (ide_hwif_t *hwif, unsigned short base)
348{
349 static unsigned long dmatable = 0;
350
351 printk(" %s: BM-DMA at 0x%04x-0x%04x", hwif->name, base, base+7);
352 if (check_region(base, 8)) {
353 printk(" -- ERROR, PORTS ALREADY IN USE");
354 } else {
355 request_region(base, 8, "IDE DMA");
356 hwif->dma_base = base;
357 if (!dmatable) {
358 /*
359 * The BM-DMA uses a full 32-bits, so we can
360 * safely use __get_free_page() here instead
361 * of __get_dma_pages() -- no ISA limitations.
362 */
363 dmatable = __get_free_pages(GFP_KERNEL0x03, 1, 0);
364 }
365 if (dmatable) {
366 hwif->dmatable = (unsigned long *) dmatable;
367 dmatable += (PRD_ENTRIES((1 << 12) / (2 * 8)) * PRD_BYTES8);
368 outl(virt_to_bus(hwif->dmatable), base + 4)((__builtin_constant_p((base + 4)) && (base + 4) <
256) ? __outlc((virt_to_phys(hwif->dmatable)),(base + 4))
: __outl((virt_to_phys(hwif->dmatable)),(base + 4)));
369 hwif->dmaproc = &triton_dmaproc;
370 }
371 }
372 printk("\n");
373}
374
375/*
376 * Set VIA Chipset Timings for (U)DMA modes enabled.
377 */
378static int set_via_timings (byte bus, byte fn, byte post, byte flush)
379{
380 byte via_config = 0;
381 int rc = 0;
382
383 /* setting IDE read prefetch buffer and IDE post write buffer */
384 if ((rc = pcibios_read_config_byte(bus, fn, 0x41, &via_config)))
385 return (1);
386 if ((rc = pcibios_write_config_byte(bus, fn, 0x41, via_config | post)))
387 return (1);
388
389 /* setting Channel read and End-of-sector FIFO flush: */
390 if ((rc = pcibios_read_config_byte(bus, fn, 0x46, &via_config)))
391 return (1);
392 if ((rc = pcibios_write_config_byte(bus, fn, 0x46, via_config | flush)))
393 return (1);
394
395 return (0);
396}
397
398static int setup_aladdin (byte bus, byte fn)
399{
400 byte confreg0 = 0, confreg1 = 0, progif = 0;
401 int errors = 0;
402
403 if (pcibios_read_config_byte(bus, fn, 0x50, &confreg1))
404 goto veryspecialsettingserror;
405 if (!(confreg1 & 0x02))
406 if (pcibios_write_config_byte(bus, fn, 0x50, confreg1 | 0x02))
407 goto veryspecialsettingserror;
408
409 if (pcibios_read_config_byte(bus, fn, 0x09, &progif))
410 goto veryspecialsettingserror;
411 if (!(progif & 0x40)) {
412 /*
413 * The way to enable them is to set progif
414 * writable at 0x4Dh register, and set bit 6
415 * of progif to 1:
416 */
417 if (pcibios_read_config_byte(bus, fn, 0x4d, &confreg0))
418 goto veryspecialsettingserror;
419 if (confreg0 & 0x80)
420 if (pcibios_write_config_byte(bus, fn, 0x4d, confreg0 & ~0x80))
421 goto veryspecialsettingserror;
422 if (pcibios_write_config_byte(bus, fn, 0x09, progif | 0x40))
423 goto veryspecialsettingserror;
424 if (confreg0 & 0x80)
425 if (pcibios_write_config_byte(bus, fn, 0x4d, confreg0))
426 errors++;
427 }
428
429 if ((pcibios_read_config_byte(bus, fn, 0x09, &progif)) || (!(progif & 0x40)))
430 goto veryspecialsettingserror;
431
432 printk("ide: ALI15X3: enabled read of IDE channels state (en/dis-abled) %s.\n",
433 errors ? "with Error(s)" : "Succeeded" );
434 return 1;
435veryspecialsettingserror:
436 printk("ide: ALI15X3: impossible to enable read of IDE channels state (en/dis-abled)!\n");
437 return 0;
438}
439
440void set_promise_hpt343_extra (unsigned short device, unsigned int bmiba)
441{
442 switch(device) {
443 case PCI_DEVICE_ID_PROMISE_202460x4d33:
444 if(!check_region((bmiba+16), 16))
445 request_region((bmiba+16), 16, "PDC20246");
446 break;
447 case PCI_DEVICE_ID_PROMISE_202620x4d38:
448 if (!check_region((bmiba+48), 48))
449 request_region((bmiba+48), 48, "PDC20262");
450 break;
451 case PCI_DEVICE_ID_TTI_HPT3430x0003:
452 if(!check_region((bmiba+16), 16))
453 request_region((bmiba+16), 16, "HPT343");
454 break;
455 default:
456 break;
457 }
458}
459
460#define HPT343_PCI_INIT_REG0x80 0x80
461
462/*
463 * ide_init_triton() prepares the IDE driver for DMA operation.
464 * This routine is called once, from ide.c during driver initialization,
465 * for each BM-DMA chipset which is found (rarely more than one).
466 */
467void ide_init_triton (byte bus, byte fn)
468{
469 byte bridgebus, bridgefn, bridgeset = 0, hpt34x_flag = 0;
470 unsigned char irq = 0;
471 int dma_enabled = 0, rc = 0, h;
472 unsigned short io[6], count = 0, step_count = 0, pass_count = 0;
473 unsigned short pcicmd, vendor, device, class;
474 unsigned int bmiba, timings, reg, tmp;
475 unsigned int addressbios = 0;
476 unsigned long flags;
477 unsigned index;
478
479#if defined(DISPLAY_APOLLO_TIMINGS) || defined(DISPLAY_ALI15X3_TIMINGS)
480 bmide_bus = bus;
481 bmide_fn = fn;
482#endif /* DISPLAY_APOLLO_TIMINGS || DISPLAY_ALI15X3_TIMINGS */
483
484/*
485 * We pick up the vendor, device, and class info for selecting the correct
486 * controller that is supported. Since we can access this routine more than
487 * once with the use of onboard and off-board EIDE controllers, a method
488 * of determining "who is who for what" is needed.
489 */
490
491 pcibios_read_config_word (bus, fn, PCI_VENDOR_ID0x00, &vendor);
492 pcibios_read_config_word (bus, fn, PCI_DEVICE_ID0x02, &device);
493 pcibios_read_config_word (bus, fn, PCI_CLASS_DEVICE0x0a, &class);
494 pcibios_read_config_byte (bus, fn, PCI_INTERRUPT_LINE0x3c, &irq);
495
496 switch(vendor) {
497 case PCI_VENDOR_ID_INTEL0x8086:
498 printk("ide: Intel 82371 ");
499 switch(device) {
500 case PCI_DEVICE_ID_INTEL_82371_00x122e:
501 printk("PIIX (single FIFO) ");
502 break;
503 case PCI_DEVICE_ID_INTEL_82371SB_10x7010:
504 printk("PIIX3 (dual FIFO) ");
505 break;
506 case PCI_DEVICE_ID_INTEL_82371AB0x7111:
507 printk("PIIX4 (dual FIFO) ");
508 break;
509 default:
510 printk(" (unknown) 0x%04x ", device);
511 break;
512 }
513 printk("DMA Bus Mastering IDE ");
514 break;
515 case PCI_VENDOR_ID_SI0x1039:
516 printk("ide: SiS 5513 (dual FIFO) DMA Bus Mastering IDE ");
517 break;
518 case PCI_VENDOR_ID_VIA0x1106:
519 printk("ide: VIA VT82C586B (split FIFO) UDMA Bus Mastering IDE ");
520 break;
521 case PCI_VENDOR_ID_TTI0x1103:
522 /*PCI_CLASS_STORAGE_UNKNOWN == class */
523 if (device == PCI_DEVICE_ID_TTI_HPT3430x0003) {
524 pcibios_write_config_byte(bus, fn, HPT343_PCI_INIT_REG0x80, 0x00);
525 pcibios_read_config_word(bus, fn, PCI_COMMAND0x04, &pcicmd);
526 hpt34x_flag = (pcicmd & PCI_COMMAND_MEMORY0x2) ? 1 : 0;
527#if 1
528 if (!hpt34x_flag) {
529 save_flags(flags)__asm__ __volatile__("pushf ; pop %0" : "=r" (flags): :"memory"
);
530 cli()__asm__ __volatile__ ("cli": : :"memory");
531 pcibios_write_config_word(bus, fn, PCI_COMMAND0x04, pcicmd & ~PCI_COMMAND_IO0x1);
532 pcibios_read_config_dword(bus, fn, PCI_BASE_ADDRESS_40x20, &bmiba);
533 pcibios_write_config_dword(bus, fn, PCI_BASE_ADDRESS_00x10, bmiba | 0x20);
534 pcibios_write_config_dword(bus, fn, PCI_BASE_ADDRESS_10x14, bmiba | 0x34);
535 pcibios_write_config_dword(bus, fn, PCI_BASE_ADDRESS_20x18, bmiba | 0x28);
536 pcibios_write_config_dword(bus, fn, PCI_BASE_ADDRESS_30x1c, bmiba | 0x3c);
537 pcibios_write_config_word(bus, fn, PCI_COMMAND0x04, pcicmd);
538 bmiba = 0;
539 restore_flags(flags)__asm__ __volatile__("push %0 ; popf": :"g" (flags):"memory");
540 }
541#endif
542 pcibios_write_config_byte(bus, fn, PCI_LATENCY_TIMER0x0d, 0x20);
543 goto hpt343_jump_in;
544 } else {
545 printk("ide: HPTXXX did == 0x%04X unsupport chipset error.\n", device);
546 return;
547 }
548 case PCI_VENDOR_ID_PROMISE0x105a:
549 /*
550 * I have been able to make my Promise Ultra33 UDMA card change class.
551 * It has reported as both PCI_CLASS_STORAGE_RAID and PCI_CLASS_STORAGE_IDE.
552 * Since the PCI_CLASS_STORAGE_RAID mode should automatically mirror the
553 * two halves of the PCI_CONFIG register data, but sometimes it forgets.
554 * Thus we guarantee that they are identical, with a quick check and
555 * correction if needed.
556 * PDC20246 (primary) PDC20247 (secondary) IDE hwif's.
557 *
558 * PDC20262 Promise Ultra66 UDMA.
559 *
560 * Note that Promise "stories,fibs,..." about this device not being
561 * capable of ATAPI and AT devices.
562 */
563 if (class != PCI_CLASS_STORAGE_IDE0x0101) {
564 unsigned char irq_mirror = 0;
565
566 pcibios_read_config_byte(bus, fn, (PCI_INTERRUPT_LINE0x3c)|0x80, &irq_mirror);
567 if (irq != irq_mirror) {
568 pcibios_write_config_byte(bus, fn, (PCI_INTERRUPT_LINE0x3c)|0x80, irq);
569 }
570 }
571 case PCI_VENDOR_ID_ARTOP0x1191:
572 /* PCI_CLASS_STORAGE_SCSI == class */
573 /*
574 * I have found that by stroking rom_enable_bit on both the AEC6210U/UF and
575 * PDC20246 controller cards, the features desired are almost guaranteed
576 * to be enabled and compatible. This ROM may not be registered in the
577 * config data, but it can be turned on. Registration failure has only
578 * been observed if and only if Linux sets up the pci_io_address in the
579 * 0x6000 range. If they are setup in the 0xef00 range it is reported.
580 * WHY??? got me.........
581 */
582hpt343_jump_in:
583 printk("ide: %s UDMA Bus Mastering ",
584 (device == PCI_DEVICE_ID_ARTOP_ATP850UF0x0005) ? "AEC6210" :
585 (device == PCI_DEVICE_ID_PROMISE_202460x4d33) ? "PDC20246" :
586 (device == PCI_DEVICE_ID_PROMISE_202620x4d38) ? "PDC20262" :
587 (hpt34x_flag && (device == PCI_DEVICE_ID_TTI_HPT3430x0003)) ? "HPT345" :
588 (device == PCI_DEVICE_ID_TTI_HPT3430x0003) ? "HPT343" : "UNKNOWN");
589 pcibios_read_config_dword(bus, fn, PCI_ROM_ADDRESS0x30, &addressbios);
590 if (addressbios) {
591 pcibios_write_config_byte(bus, fn, PCI_ROM_ADDRESS0x30, addressbios | PCI_ROM_ADDRESS_ENABLE0x01);
592 printk("with ROM enabled at 0x%08x", addressbios);
593 }
594 /*
595 * This was stripped out of 2.1.XXX kernel code and parts from a patch called
596 * promise_update. This finds the PCI_BASE_ADDRESS spaces and makes them
597 * available for configuration later.
598 * PCI_BASE_ADDRESS_0 hwif0->io_base
599 * PCI_BASE_ADDRESS_1 hwif0->ctl_port
600 * PCI_BASE_ADDRESS_2 hwif1->io_base
601 * PCI_BASE_ADDRESS_3 hwif1->ctl_port
602 * PCI_BASE_ADDRESS_4 bmiba
603 */
604 memset(io, 0, 6 * sizeof(unsigned short))(__builtin_constant_p(0) ? (__builtin_constant_p((6 * sizeof(
unsigned short))) ? __constant_c_and_count_memset(((io)),((0x01010101UL
*(unsigned char)(0))),((6 * sizeof(unsigned short)))) : __constant_c_memset
(((io)),((0x01010101UL*(unsigned char)(0))),((6 * sizeof(unsigned
short))))) : (__builtin_constant_p((6 * sizeof(unsigned short
))) ? __memset_generic((((io))),(((0))),(((6 * sizeof(unsigned
short))))) : __memset_generic(((io)),((0)),((6 * sizeof(unsigned
short))))));
605 for (reg = PCI_BASE_ADDRESS_00x10; reg <= PCI_BASE_ADDRESS_50x24; reg += 4) {
606 pcibios_read_config_dword(bus, fn, reg, &tmp);
607 if (tmp & PCI_BASE_ADDRESS_SPACE_IO0x01)
608 io[count++] = tmp & PCI_BASE_ADDRESS_IO_MASK(~0x03);
609 }
610 break;
611 case PCI_VENDOR_ID_AL0x10b9:
612 save_flags(flags)__asm__ __volatile__("pushf ; pop %0" : "=r" (flags): :"memory"
);
613 cli()__asm__ __volatile__ ("cli": : :"memory");
614 for (index = 0; !pcibios_find_device (PCI_VENDOR_ID_AL0x10b9, PCI_DEVICE_ID_AL_M15330x1533, index, &bridgebus, &bridgefn); ++index) {
615 bridgeset = setup_aladdin(bus, fn);
616 }
617 restore_flags(flags)__asm__ __volatile__("push %0 ; popf": :"g" (flags):"memory");
618 printk("ide: ALI15X3 (dual FIFO) DMA Bus Mastering IDE ");
619 break;
620 default:
621 return;
622 }
623
624 printk("\n Controller on PCI bus %d function %d\n", bus, fn);
625
626 /*
627 * See if IDE and BM-DMA features are enabled:
628 */
629 if ((rc = pcibios_read_config_word(bus, fn, PCI_COMMAND0x04, &pcicmd)))
630 goto quit;
631 if ((pcicmd & 1) == 0) {
632 printk("ide: ports are not enabled (BIOS)\n");
633 goto quit;
634 }
635 if ((pcicmd & 4) == 0) {
636 printk("ide: BM-DMA feature is not enabled (BIOS), enabling\n");
637 pcicmd |= 4;
638 pcibios_write_config_word(bus, fn, 0x04, pcicmd);
639 if ((rc = pcibios_read_config_word(bus, fn, 0x04, &pcicmd))) {
640 printk("ide: Couldn't read back PCI command\n");
641 goto quit;
642 }
643 }
644
645 if ((pcicmd & 4) == 0) {
646 printk("ide: BM-DMA feature couldn't be enabled\n");
647 } else {
648 /*
649 * Get the bmiba base address
650 */
651 int try_again = 1;
652 do {
653 if ((rc = pcibios_read_config_dword(bus, fn, PCI_BASE_ADDRESS_40x20, &bmiba)))
654 goto quit;
655 bmiba &= 0xfff0; /* extract port base address */
656 if (bmiba) {
657 dma_enabled = 1;
658 break;
659 } else {
660 printk("ide: BM-DMA base register is invalid (0x%04x, PnP BIOS problem)\n", bmiba);
661 if (inb(((vendor == PCI_VENDOR_ID_AL) ? DEFAULT_BMALIBA :((__builtin_constant_p((((vendor == 0x10b9) ? 0xd400 : (vendor
== 0x1106) ? 0xcc00 : 0xe800))) && (((vendor == 0x10b9
) ? 0xd400 : (vendor == 0x1106) ? 0xcc00 : 0xe800)) < 256)
? __inbc(((vendor == 0x10b9) ? 0xd400 : (vendor == 0x1106) ?
0xcc00 : 0xe800)) : __inb(((vendor == 0x10b9) ? 0xd400 : (vendor
== 0x1106) ? 0xcc00 : 0xe800)))
662 (vendor == PCI_VENDOR_ID_VIA) ? DEFAULT_BMCRBA :((__builtin_constant_p((((vendor == 0x10b9) ? 0xd400 : (vendor
== 0x1106) ? 0xcc00 : 0xe800))) && (((vendor == 0x10b9
) ? 0xd400 : (vendor == 0x1106) ? 0xcc00 : 0xe800)) < 256)
? __inbc(((vendor == 0x10b9) ? 0xd400 : (vendor == 0x1106) ?
0xcc00 : 0xe800)) : __inb(((vendor == 0x10b9) ? 0xd400 : (vendor
== 0x1106) ? 0xcc00 : 0xe800)))
663 DEFAULT_BMIBA))((__builtin_constant_p((((vendor == 0x10b9) ? 0xd400 : (vendor
== 0x1106) ? 0xcc00 : 0xe800))) && (((vendor == 0x10b9
) ? 0xd400 : (vendor == 0x1106) ? 0xcc00 : 0xe800)) < 256)
? __inbc(((vendor == 0x10b9) ? 0xd400 : (vendor == 0x1106) ?
0xcc00 : 0xe800)) : __inb(((vendor == 0x10b9) ? 0xd400 : (vendor
== 0x1106) ? 0xcc00 : 0xe800))) != 0xff || !try_again)
664 break;
665 printk("ide: setting BM-DMA base register to 0x%04x\n",
666 ((vendor == PCI_VENDOR_ID_AL0x10b9) ? DEFAULT_BMALIBA0xd400 :
667 (vendor == PCI_VENDOR_ID_VIA0x1106) ? DEFAULT_BMCRBA0xcc00 :
668 DEFAULT_BMIBA0xe800));
669 if ((rc = pcibios_write_config_word(bus, fn, PCI_COMMAND0x04, pcicmd&~1)))
670 goto quit;
671 rc = pcibios_write_config_dword(bus, fn, 0x20,
672 ((vendor == PCI_VENDOR_ID_AL0x10b9) ? DEFAULT_BMALIBA0xd400 :
673 (vendor == PCI_VENDOR_ID_VIA0x1106) ? DEFAULT_BMCRBA0xcc00 :
674 DEFAULT_BMIBA0xe800)|1);
675 if (pcibios_write_config_word(bus, fn, PCI_COMMAND0x04, pcicmd|5) || rc)
676 goto quit;
677 }
678 } while (try_again--);
679 }
680
681 /*
682 * See if ide port(s) are enabled
683 */
684 if ((rc = pcibios_read_config_dword(bus, fn,
685 (vendor == PCI_VENDOR_ID_PROMISE0x105a) ? 0x50 :
686 (vendor == PCI_VENDOR_ID_ARTOP0x1191) ? 0x54 :
687 (vendor == PCI_VENDOR_ID_SI0x1039) ? 0x48 :
688 (vendor == PCI_VENDOR_ID_AL0x10b9) ? 0x08 :
689 0x40, &timings)))
690 goto quit;
691 /*
692 * We do a vendor check since the Ultra33/66 and AEC6210
693 * holds their timings in a different location.
694 */
695#if 0
696 printk("ide: timings == %08x\n", timings);
697#endif
698 /*
699 * The switch preserves some stuff that was original.
700 */
701 switch(vendor) {
702 case PCI_VENDOR_ID_INTEL0x8086:
703 if (!(timings & 0x80008000)) {
704 printk("ide: INTEL: neither port is enabled\n");
705 goto quit;
706 }
707 break;
708 case PCI_VENDOR_ID_VIA0x1106:
709 if(!(timings & 0x03)) {
710 printk("ide: VIA: neither port is enabled\n");
711 goto quit;
712 }
713 break;
714 case PCI_VENDOR_ID_AL0x10b9:
715 timings <<= 16;
716 timings >>= 24;
717 if (!(timings & 0x30)) {
718 printk("ide: ALI15X3: neither port is enabled\n");
719 goto quit;
720 }
721 break;
722 case PCI_VENDOR_ID_SI0x1039:
723 timings <<= 8;
724 timings >>= 24;
725 if (!(timings & 0x06)) {
726 printk("ide: SIS5513: neither port is enabled\n");
727 goto quit;
728 }
729 break;
730 case PCI_VENDOR_ID_PROMISE0x105a:
731 printk(" (U)DMA Burst Bit %sABLED " \
732 "Primary %s Mode " \
733 "Secondary %s Mode.\n",
734 (inb(bmiba + 0x001f)((__builtin_constant_p((bmiba + 0x001f)) && (bmiba + 0x001f
) < 256) ? __inbc(bmiba + 0x001f) : __inb(bmiba + 0x001f)) & 1) ? "EN" : "DIS",
735 (inb(bmiba + 0x001a)((__builtin_constant_p((bmiba + 0x001a)) && (bmiba + 0x001a
) < 256) ? __inbc(bmiba + 0x001a) : __inb(bmiba + 0x001a)) & 1) ? "MASTER" : "PCI",
736 (inb(bmiba + 0x001b)((__builtin_constant_p((bmiba + 0x001b)) && (bmiba + 0x001b
) < 256) ? __inbc(bmiba + 0x001b) : __inb(bmiba + 0x001b)) & 1) ? "MASTER" : "PCI" );
737#if 0
738 if (!(inb(bmiba + 0x001f)((__builtin_constant_p((bmiba + 0x001f)) && (bmiba + 0x001f
) < 256) ? __inbc(bmiba + 0x001f) : __inb(bmiba + 0x001f)) & 1)) {
739 outb(inb(bmiba + 0x001f)|0x01, (bmiba + 0x001f))((__builtin_constant_p(((bmiba + 0x001f))) && ((bmiba
+ 0x001f)) < 256) ? __outbc((((__builtin_constant_p((bmiba
+ 0x001f)) && (bmiba + 0x001f) < 256) ? __inbc(bmiba
+ 0x001f) : __inb(bmiba + 0x001f))|0x01),((bmiba + 0x001f)))
: __outb((((__builtin_constant_p((bmiba + 0x001f)) &&
(bmiba + 0x001f) < 256) ? __inbc(bmiba + 0x001f) : __inb(
bmiba + 0x001f))|0x01),((bmiba + 0x001f))));
740 printk(" (U)DMA Burst Bit Forced %sABLED.\n",
741 (inb(bmiba + 0x001f)((__builtin_constant_p((bmiba + 0x001f)) && (bmiba + 0x001f
) < 256) ? __inbc(bmiba + 0x001f) : __inb(bmiba + 0x001f)) & 1) ? "EN" : "DIS");
742 }
743#endif
744 break;
745 case PCI_VENDOR_ID_ARTOP0x1191:
746 case PCI_VENDOR_ID_TTI0x1103:
747 default:
748 break;
749 }
750
751 /*
752 * Save the dma_base port addr for each interface
753 */
754 for (h = 0; h < MAX_HWIFS4; ++h) {
755 ide_hwif_t *hwif = &ide_hwifs[h];
756 byte channel = ((h == 1) || (h == 3) || (h == 5)) ? 1 : 0;
757
758 /*
759 * This prevents the first contoller from accidentally
760 * initalizing the hwif's that it does not use and block
761 * an off-board ide-pci from getting in the game.
762 */
763 if ((step_count >= 2) || (pass_count >= 2)) {
764 goto quit;
765 }
766
767#if 0
768 if (hwif->chipset == ide_unknown)
769 printk("ide: index == %d channel(%d)\n", h, channel);
770#endif
771
772#ifdef CONFIG_BLK_DEV_OFFBOARD
773 /*
774 * This is a forced override for the onboard ide controller
775 * to be enabled, if one chooses to have an offboard ide-pci
776 * card as the primary booting device. This beasty is
777 * for offboard UDMA upgrades with hard disks, but saving
778 * the onboard DMA2 controllers for CDROMS, TAPES, ZIPS, etc...
779 */
780 if (((vendor == PCI_VENDOR_ID_INTEL0x8086) ||
781 (vendor == PCI_VENDOR_ID_SI0x1039) ||
782 (vendor == PCI_VENDOR_ID_VIA0x1106) ||
783 (vendor == PCI_VENDOR_ID_AL0x10b9)) && (h >= 2)) {
784 hwif->io_base = channel ? 0x170 : 0x1f0;
785 hwif->ctl_port = channel ? 0x376 : 0x3f6;
786 hwif->irq = channel ? 15 : 14;
787 hwif->noprobe = 0;
788 }
789#endif /* CONFIG_BLK_DEV_OFFBOARD */
790 /*
791 * If the chipset is listed as "ide_unknown", lets get a
792 * hwif while they last. This does the first check on
793 * the current availability of the ide_hwifs[h] in question.
794 */
795 if (hwif->chipset != ide_unknown) {
796 continue;
797 } else if (vendor == PCI_VENDOR_ID_INTEL0x8086) {
798 unsigned short time;
799#ifdef DISPLAY_TRITON_TIMINGS
800 byte s_clks, r_clks;
801 unsigned short devid;
802#endif /* DISPLAY_TRITON_TIMINGS */
803 pass_count++;
804 if (hwif->io_base == 0x1f0) {
805 time = timings & 0xffff;
806 if ((time & 0x8000) == 0) /* interface enabled? */
807 continue;
808 hwif->chipset = ide_triton;
809 if (dma_enabled)
810 init_triton_dma(hwif, bmiba);
811 step_count++;
812 } else if (hwif->io_base == 0x170) {
813 time = timings >> 16;
814 if ((time & 0x8000) == 0) /* interface enabled? */
815 continue;
816 hwif->chipset = ide_triton;
817 if (dma_enabled)
818 init_triton_dma(hwif, bmiba + 8);
819 step_count++;
820 } else {
821 continue;
822 }
823#ifdef DISPLAY_TRITON_TIMINGS
824 s_clks = ((~time >> 12) & 3) + 2;
825 r_clks = ((~time >> 8) & 3) + 1;
826 printk(" %s timing: (0x%04x) sample_CLKs=%d, recovery_CLKs=%d\n",
827 hwif->name, time, s_clks, r_clks);
828 if ((time & 0x40) && !pcibios_read_config_word(bus, fn, PCI_DEVICE_ID0x02, &devid)
829 && devid == PCI_DEVICE_ID_INTEL_82371SB_10x7010) {
830 byte stime;
831 if (pcibios_read_config_byte(bus, fn, 0x44, &stime)) {
832 if (hwif->io_base == 0x1f0) {
833 s_clks = ~stime >> 6;
834 r_clks = ~stime >> 4;
835 } else {
836 s_clks = ~stime >> 2;
837 r_clks = ~stime;
838 }
839 s_clks = (s_clks & 3) + 2;
840 r_clks = (r_clks & 3) + 1;
841 printk(" slave: sample_CLKs=%d, recovery_CLKs=%d\n",
842 s_clks, r_clks);
843 }
844 }
845 print_triton_drive_flags (0, time & 0xf);
846 print_triton_drive_flags (1, (time >> 4) & 0xf);
847#endif /* DISPLAY_TRITON_TIMINGS */
848 } else if (vendor == PCI_VENDOR_ID_SI0x1039) {
849 pass_count++;
850 if (hwif->io_base == 0x1f0) {
851 if ((timings & 0x02) == 0)
852 continue;
853 hwif->chipset = ide_triton;
854 if (dma_enabled)
855 init_triton_dma(hwif, bmiba);
856 step_count++;
857 } else if (hwif->io_base == 0x170) {
858 if ((timings & 0x04) == 0)
859 continue;
860 hwif->chipset = ide_triton;
861 if (dma_enabled)
862 init_triton_dma(hwif, bmiba + 8);
863 step_count++;
864 } else {
865 continue;
866 }
867 } else if (vendor == PCI_VENDOR_ID_VIA0x1106) {
868 pass_count++;
869 if (hwif->io_base == 0x1f0) {
870 if ((timings & 0x02) == 0)
871 continue;
872 hwif->chipset = ide_triton;
873 if (dma_enabled)
874 init_triton_dma(hwif, bmiba);
875 if (set_via_timings(bus, fn, 0xc0, 0xa0))
876 goto quit;
877#ifdef DISPLAY_APOLLO_TIMINGS
878 proc_register_dynamic(&proc_root, &via_proc_entry);
879#endif /* DISPLAY_APOLLO_TIMINGS */
880 step_count++;
881 } else if (hwif->io_base == 0x170) {
882 if ((timings & 0x01) == 0)
883 continue;
884 hwif->chipset = ide_triton;
885 if (dma_enabled)
886 init_triton_dma(hwif, bmiba + 8);
887 if (set_via_timings(bus, fn, 0x30, 0x50))
888 goto quit;
889 step_count++;
890 } else {
891 continue;
892 }
893 } else if (vendor == PCI_VENDOR_ID_AL0x10b9) {
894 byte ideic, inmir;
895 byte irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
896 1, 11, 0, 12, 0, 14, 0, 15 };
897
898 if (bridgeset) {
899 pcibios_read_config_byte(bridgebus, bridgefn, 0x58, &ideic);
900 ideic = ideic & 0x03;
901 if ((channel && ideic == 0x03) || (!channel && !ideic)) {
902 pcibios_read_config_byte(bridgebus, bridgefn, 0x44, &inmir);
903 inmir = inmir & 0x0f;
904 hwif->irq = irq_routing_table[inmir];
905 } else if (channel && !(ideic & 0x01)) {
906 pcibios_read_config_byte(bridgebus, bridgefn, 0x75, &inmir);
907 inmir = inmir & 0x0f;
908 hwif->irq = irq_routing_table[inmir];
909 }
910 }
911 pass_count++;
912 if (hwif->io_base == 0x1f0) {
913 if ((timings & 0x20) == 0)
914 continue;
915 hwif->chipset = ide_triton;
916 if (dma_enabled)
917 init_triton_dma(hwif, bmiba);
918 outb(inb(bmiba+2) & 0x60, bmiba+2)((__builtin_constant_p((bmiba+2)) && (bmiba+2) < 256
) ? __outbc((((__builtin_constant_p((bmiba+2)) && (bmiba
+2) < 256) ? __inbc(bmiba+2) : __inb(bmiba+2)) & 0x60)
,(bmiba+2)) : __outb((((__builtin_constant_p((bmiba+2)) &&
(bmiba+2) < 256) ? __inbc(bmiba+2) : __inb(bmiba+2)) &
0x60),(bmiba+2)));
919 if (inb(bmiba+2)((__builtin_constant_p((bmiba+2)) && (bmiba+2) < 256
) ? __inbc(bmiba+2) : __inb(bmiba+2)) & 0x80)
920 printk("ALI15X3: simplex device: DMA forced\n");
921#ifdef DISPLAY_ALI15X3_TIMINGS
922 proc_register_dynamic(&proc_root, &ali_proc_entry);
923#endif /* DISPLAY_ALI15X3_TIMINGS */
924 step_count++;
925 } else if (hwif->io_base == 0x170) {
926 if ((timings & 0x10) == 0)
927 continue;
928 hwif->chipset = ide_triton;
929 if (dma_enabled)
930 init_triton_dma(hwif, bmiba + 8);
931 outb(inb(bmiba+10) & 0x60, bmiba+10)((__builtin_constant_p((bmiba+10)) && (bmiba+10) <
256) ? __outbc((((__builtin_constant_p((bmiba+10)) &&
(bmiba+10) < 256) ? __inbc(bmiba+10) : __inb(bmiba+10)) &
0x60),(bmiba+10)) : __outb((((__builtin_constant_p((bmiba+10
)) && (bmiba+10) < 256) ? __inbc(bmiba+10) : __inb
(bmiba+10)) & 0x60),(bmiba+10)));
932 if (inb(bmiba+10)((__builtin_constant_p((bmiba+10)) && (bmiba+10) <
256) ? __inbc(bmiba+10) : __inb(bmiba+10)) & 0x80)
933 printk("ALI15X3: simplex device: DMA forced\n");
934 step_count++;
935 } else {
936 continue;
937 }
938 } else if ((vendor == PCI_VENDOR_ID_PROMISE0x105a) ||
939 (vendor == PCI_VENDOR_ID_ARTOP0x1191) ||
940 (vendor == PCI_VENDOR_ID_TTI0x1103)) {
941 pass_count++;
942 if (vendor == PCI_VENDOR_ID_TTI0x1103) {
943 if ((!hpt34x_flag) && (h < 2)) {
944 goto quit;
945 } else if (hpt34x_flag) {
946 hwif->io_base = channel ? (bmiba + 0x28) : (bmiba + 0x20);
947 hwif->ctl_port = channel ? (bmiba + 0x3e) : (bmiba + 0x36);
948 } else {
949 goto io_temps;
950 }
951 } else {
952io_temps:
953 tmp = channel ? 2 : 0;
954 hwif->io_base = io[tmp];
955 hwif->ctl_port = io[tmp + 1] + 2;
956 }
957 hwif->irq = irq;
958 hwif->noprobe = 0;
959
960 if (device == PCI_DEVICE_ID_ARTOP_ATP850UF0x0005) {
961 hwif->serialized = 1;
962 }
963
964 if ((vendor == PCI_VENDOR_ID_PROMISE0x105a) ||
965 (vendor == PCI_VENDOR_ID_TTI0x1103)) {
966 set_promise_hpt343_extra(device, bmiba);
967 }
968
969 if (dma_enabled) {
970 if ((!check_region(bmiba, 8)) && (!channel)) {
971 hwif->chipset = ((vendor == PCI_VENDOR_ID_TTI0x1103) && !hpt34x_flag) ? ide_hpt343 :
972 (device == PCI_DEVICE_ID_PROMISE_202620x4d38) ? ide_ultra66 : ide_udma;
973 init_triton_dma(hwif, bmiba);
974 step_count++;
975 } else if ((!check_region((bmiba + 0x08), 8)) && (channel)) {
976 hwif->chipset = ((vendor == PCI_VENDOR_ID_TTI0x1103) && !hpt34x_flag) ? ide_hpt343 :
977 (device == PCI_DEVICE_ID_PROMISE_202620x4d38) ? ide_ultra66 : ide_udma;
978 init_triton_dma(hwif, bmiba + 8);
979 step_count++;
980 } else {
981 continue;
982 }
983 }
984 }
985 }
986
987 quit: if (rc) printk("ide: pcibios access failed - %s\n", pcibios_strerror(rc));
988}