From 7996a3d79d55b7f879dfd62e202bbfe2963718d3 Mon Sep 17 00:00:00 2001 From: Samuel Thibault Date: Sat, 27 Jul 2013 22:15:01 +0000 Subject: really properly move files --- libdde-linux26/contrib/arch/arm/kernel/ptrace.h | 51 + libdde-linux26/contrib/arch/arm/kernel/signal.h | 12 + libdde-linux26/contrib/arch/arm/kernel/traps.c | 734 +++++++++ libdde-linux26/contrib/arch/arm/lib/bitops.h | 65 + libdde-linux26/contrib/arch/arm/lib/changebit.S | 23 + libdde-linux26/contrib/arch/arm/lib/clearbit.S | 24 + libdde-linux26/contrib/arch/arm/lib/div64.S | 201 +++ libdde-linux26/contrib/arch/arm/lib/findbit.S | 176 +++ libdde-linux26/contrib/arch/arm/lib/memzero.S | 125 ++ libdde-linux26/contrib/arch/arm/lib/setbit.S | 24 + .../contrib/arch/arm/lib/testchangebit.S | 20 + libdde-linux26/contrib/arch/arm/lib/testclearbit.S | 20 + libdde-linux26/contrib/arch/arm/lib/testsetbit.S | 20 + .../contrib/arch/arm/mach-realview/clock.c | 64 + .../contrib/arch/arm/mach-realview/clock.h | 19 + .../contrib/arch/arm/mach-realview/core.h | 66 + .../contrib/arch/arm/mach-realview/realview_eb.c | 389 +++++ libdde-linux26/contrib/arch/x86/include/Makefile | 13 + libdde-linux26/contrib/arch/x86/include/asm/Kbuild | 24 + .../contrib/arch/x86/include/asm/a.out-core.h | 71 + .../contrib/arch/x86/include/asm/a.out.h | 20 + libdde-linux26/contrib/arch/x86/include/asm/acpi.h | 177 +++ libdde-linux26/contrib/arch/x86/include/asm/agp.h | 35 + .../contrib/arch/x86/include/asm/alternative-asm.h | 22 + .../contrib/arch/x86/include/asm/alternative.h | 183 +++ .../contrib/arch/x86/include/asm/amd_iommu.h | 35 + .../contrib/arch/x86/include/asm/amd_iommu_types.h | 427 +++++ libdde-linux26/contrib/arch/x86/include/asm/apic.h | 199 +++ .../contrib/arch/x86/include/asm/apicdef.h | 417 +++++ .../contrib/arch/x86/include/asm/arch_hooks.h | 26 + libdde-linux26/contrib/arch/x86/include/asm/asm.h | 47 + .../contrib/arch/x86/include/asm/atomic.h | 5 + .../contrib/arch/x86/include/asm/atomic_32.h | 251 +++ .../contrib/arch/x86/include/asm/atomic_64.h | 459 ++++++ .../contrib/arch/x86/include/asm/auxvec.h | 12 + .../contrib/arch/x86/include/asm/bigsmp/apic.h | 155 ++ .../contrib/arch/x86/include/asm/bigsmp/apicdef.h | 13 + .../contrib/arch/x86/include/asm/bigsmp/ipi.h | 22 + .../contrib/arch/x86/include/asm/bios_ebda.h | 36 + .../contrib/arch/x86/include/asm/bitops.h | 465 ++++++ libdde-linux26/contrib/arch/x86/include/asm/boot.h | 26 + .../contrib/arch/x86/include/asm/bootparam.h | 111 ++ libdde-linux26/contrib/arch/x86/include/asm/bug.h | 39 + libdde-linux26/contrib/arch/x86/include/asm/bugs.h | 12 + .../contrib/arch/x86/include/asm/byteorder.h | 6 + .../contrib/arch/x86/include/asm/cache.h | 20 + .../contrib/arch/x86/include/asm/cacheflush.h | 118 ++ .../contrib/arch/x86/include/asm/calgary.h | 72 + .../contrib/arch/x86/include/asm/calling.h | 170 ++ .../contrib/arch/x86/include/asm/checksum.h | 5 + .../contrib/arch/x86/include/asm/checksum_32.h | 189 +++ .../contrib/arch/x86/include/asm/checksum_64.h | 191 +++ .../contrib/arch/x86/include/asm/cmpxchg.h | 5 + .../contrib/arch/x86/include/asm/cmpxchg_32.h | 344 ++++ .../contrib/arch/x86/include/asm/cmpxchg_64.h | 185 +++ .../contrib/arch/x86/include/asm/compat.h | 218 +++ libdde-linux26/contrib/arch/x86/include/asm/cpu.h | 20 + .../contrib/arch/x86/include/asm/cpufeature.h | 275 ++++ .../contrib/arch/x86/include/asm/cputime.h | 1 + .../contrib/arch/x86/include/asm/current.h | 39 + .../contrib/arch/x86/include/asm/debugreg.h | 70 + .../contrib/arch/x86/include/asm/delay.h | 31 + libdde-linux26/contrib/arch/x86/include/asm/desc.h | 407 +++++ .../contrib/arch/x86/include/asm/desc_defs.h | 95 ++ .../contrib/arch/x86/include/asm/device.h | 16 + .../contrib/arch/x86/include/asm/div64.h | 60 + .../contrib/arch/x86/include/asm/dma-mapping.h | 306 ++++ libdde-linux26/contrib/arch/x86/include/asm/dma.h | 318 ++++ libdde-linux26/contrib/arch/x86/include/asm/dmi.h | 26 + libdde-linux26/contrib/arch/x86/include/asm/ds.h | 272 ++++ .../contrib/arch/x86/include/asm/dwarf2.h | 96 ++ libdde-linux26/contrib/arch/x86/include/asm/e820.h | 147 ++ libdde-linux26/contrib/arch/x86/include/asm/edac.h | 18 + libdde-linux26/contrib/arch/x86/include/asm/efi.h | 109 ++ libdde-linux26/contrib/arch/x86/include/asm/elf.h | 336 ++++ .../arch/x86/include/asm/emergency-restart.h | 20 + .../contrib/arch/x86/include/asm/errno.h | 1 + .../contrib/arch/x86/include/asm/es7000/apic.h | 242 +++ .../contrib/arch/x86/include/asm/es7000/apicdef.h | 13 + .../contrib/arch/x86/include/asm/es7000/ipi.h | 22 + .../contrib/arch/x86/include/asm/es7000/mpparse.h | 29 + .../contrib/arch/x86/include/asm/es7000/wakecpu.h | 37 + libdde-linux26/contrib/arch/x86/include/asm/fb.h | 21 + .../contrib/arch/x86/include/asm/fcntl.h | 1 + .../contrib/arch/x86/include/asm/fixmap.h | 72 + .../contrib/arch/x86/include/asm/fixmap_32.h | 119 ++ .../contrib/arch/x86/include/asm/fixmap_64.h | 79 + .../contrib/arch/x86/include/asm/floppy.h | 281 ++++ .../contrib/arch/x86/include/asm/frame.h | 27 + .../contrib/arch/x86/include/asm/ftrace.h | 83 + .../contrib/arch/x86/include/asm/futex.h | 140 ++ libdde-linux26/contrib/arch/x86/include/asm/gart.h | 106 ++ .../contrib/arch/x86/include/asm/genapic.h | 5 + .../contrib/arch/x86/include/asm/genapic_32.h | 148 ++ .../contrib/arch/x86/include/asm/genapic_64.h | 66 + .../contrib/arch/x86/include/asm/geode.h | 253 +++ libdde-linux26/contrib/arch/x86/include/asm/gpio.h | 56 + .../contrib/arch/x86/include/asm/hardirq.h | 11 + .../contrib/arch/x86/include/asm/hardirq_32.h | 30 + .../contrib/arch/x86/include/asm/hardirq_64.h | 25 + .../contrib/arch/x86/include/asm/highmem.h | 79 + libdde-linux26/contrib/arch/x86/include/asm/hpet.h | 114 ++ .../contrib/arch/x86/include/asm/hugetlb.h | 93 ++ .../contrib/arch/x86/include/asm/hw_irq.h | 129 ++ .../contrib/arch/x86/include/asm/hypertransport.h | 45 + .../contrib/arch/x86/include/asm/hypervisor.h | 26 + libdde-linux26/contrib/arch/x86/include/asm/i387.h | 406 +++++ .../contrib/arch/x86/include/asm/i8253.h | 18 + .../contrib/arch/x86/include/asm/i8259.h | 63 + libdde-linux26/contrib/arch/x86/include/asm/ia32.h | 152 ++ .../contrib/arch/x86/include/asm/ia32_unistd.h | 18 + libdde-linux26/contrib/arch/x86/include/asm/idle.h | 21 + .../arch/x86/include/asm/intel_arch_perfmon.h | 31 + libdde-linux26/contrib/arch/x86/include/asm/io.h | 109 ++ .../contrib/arch/x86/include/asm/io_32.h | 284 ++++ .../contrib/arch/x86/include/asm/io_64.h | 242 +++ .../contrib/arch/x86/include/asm/io_apic.h | 211 +++ .../contrib/arch/x86/include/asm/ioctl.h | 1 + .../contrib/arch/x86/include/asm/ioctls.h | 94 ++ .../contrib/arch/x86/include/asm/iomap.h | 33 + .../contrib/arch/x86/include/asm/iommu.h | 13 + .../contrib/arch/x86/include/asm/ipcbuf.h | 28 + libdde-linux26/contrib/arch/x86/include/asm/ipi.h | 157 ++ libdde-linux26/contrib/arch/x86/include/asm/irq.h | 47 + .../contrib/arch/x86/include/asm/irq_regs.h | 5 + .../contrib/arch/x86/include/asm/irq_regs_32.h | 31 + .../contrib/arch/x86/include/asm/irq_regs_64.h | 1 + .../contrib/arch/x86/include/asm/irq_remapping.h | 8 + .../contrib/arch/x86/include/asm/irq_vectors.h | 167 ++ .../contrib/arch/x86/include/asm/irqflags.h | 211 +++ libdde-linux26/contrib/arch/x86/include/asm/ist.h | 34 + libdde-linux26/contrib/arch/x86/include/asm/k8.h | 15 + .../contrib/arch/x86/include/asm/kdebug.h | 37 + .../contrib/arch/x86/include/asm/kexec.h | 176 +++ libdde-linux26/contrib/arch/x86/include/asm/kgdb.h | 79 + .../contrib/arch/x86/include/asm/kmap_types.h | 29 + .../contrib/arch/x86/include/asm/kprobes.h | 88 ++ libdde-linux26/contrib/arch/x86/include/asm/kvm.h | 218 +++ .../contrib/arch/x86/include/asm/kvm_host.h | 762 +++++++++ .../contrib/arch/x86/include/asm/kvm_para.h | 147 ++ .../contrib/arch/x86/include/asm/kvm_x86_emulate.h | 181 +++ libdde-linux26/contrib/arch/x86/include/asm/ldt.h | 40 + .../contrib/arch/x86/include/asm/lguest.h | 94 ++ .../contrib/arch/x86/include/asm/lguest_hcall.h | 71 + .../contrib/arch/x86/include/asm/linkage.h | 121 ++ .../contrib/arch/x86/include/asm/local.h | 235 +++ .../arch/x86/include/asm/mach-default/apm.h | 73 + .../arch/x86/include/asm/mach-default/do_timer.h | 16 + .../arch/x86/include/asm/mach-default/entry_arch.h | 36 + .../arch/x86/include/asm/mach-default/mach_apic.h | 168 ++ .../x86/include/asm/mach-default/mach_apicdef.h | 24 + .../arch/x86/include/asm/mach-default/mach_ipi.h | 64 + .../x86/include/asm/mach-default/mach_mpparse.h | 17 + .../x86/include/asm/mach-default/mach_mpspec.h | 12 + .../arch/x86/include/asm/mach-default/mach_timer.h | 48 + .../arch/x86/include/asm/mach-default/mach_traps.h | 33 + .../x86/include/asm/mach-default/mach_wakecpu.h | 41 + .../x86/include/asm/mach-default/pci-functions.h | 19 + .../arch/x86/include/asm/mach-default/setup_arch.h | 3 + .../x86/include/asm/mach-default/smpboot_hooks.h | 61 + .../arch/x86/include/asm/mach-generic/gpio.h | 15 + .../arch/x86/include/asm/mach-generic/mach_apic.h | 35 + .../x86/include/asm/mach-generic/mach_apicdef.h | 11 + .../arch/x86/include/asm/mach-generic/mach_ipi.h | 10 + .../x86/include/asm/mach-generic/mach_mpparse.h | 9 + .../x86/include/asm/mach-generic/mach_mpspec.h | 12 + .../x86/include/asm/mach-generic/mach_wakecpu.h | 12 + .../arch/x86/include/asm/mach-rdc321x/gpio.h | 60 + .../x86/include/asm/mach-rdc321x/rdc321x_defs.h | 12 + .../arch/x86/include/asm/mach-voyager/do_timer.h | 17 + .../arch/x86/include/asm/mach-voyager/entry_arch.h | 26 + .../arch/x86/include/asm/mach-voyager/setup_arch.h | 12 + .../contrib/arch/x86/include/asm/math_emu.h | 18 + .../contrib/arch/x86/include/asm/mc146818rtc.h | 104 ++ libdde-linux26/contrib/arch/x86/include/asm/mca.h | 43 + .../contrib/arch/x86/include/asm/mca_dma.h | 201 +++ libdde-linux26/contrib/arch/x86/include/asm/mce.h | 127 ++ .../contrib/arch/x86/include/asm/microcode.h | 47 + libdde-linux26/contrib/arch/x86/include/asm/mman.h | 20 + .../contrib/arch/x86/include/asm/mmconfig.h | 12 + libdde-linux26/contrib/arch/x86/include/asm/mmu.h | 26 + .../contrib/arch/x86/include/asm/mmu_context.h | 37 + .../contrib/arch/x86/include/asm/mmu_context_32.h | 55 + .../contrib/arch/x86/include/asm/mmu_context_64.h | 54 + libdde-linux26/contrib/arch/x86/include/asm/mmx.h | 14 + .../contrib/arch/x86/include/asm/mmzone.h | 5 + .../contrib/arch/x86/include/asm/mmzone_32.h | 136 ++ .../contrib/arch/x86/include/asm/mmzone_64.h | 49 + .../contrib/arch/x86/include/asm/module.h | 80 + .../contrib/arch/x86/include/asm/mpspec.h | 151 ++ .../contrib/arch/x86/include/asm/mpspec_def.h | 180 +++ .../contrib/arch/x86/include/asm/msgbuf.h | 39 + .../contrib/arch/x86/include/asm/msidef.h | 55 + .../contrib/arch/x86/include/asm/msr-index.h | 363 +++++ libdde-linux26/contrib/arch/x86/include/asm/msr.h | 246 +++ libdde-linux26/contrib/arch/x86/include/asm/mtrr.h | 199 +++ .../contrib/arch/x86/include/asm/mutex.h | 5 + .../contrib/arch/x86/include/asm/mutex_32.h | 125 ++ .../contrib/arch/x86/include/asm/mutex_64.h | 100 ++ libdde-linux26/contrib/arch/x86/include/asm/nmi.h | 81 + libdde-linux26/contrib/arch/x86/include/asm/nops.h | 118 ++ libdde-linux26/contrib/arch/x86/include/asm/numa.h | 5 + .../contrib/arch/x86/include/asm/numa_32.h | 11 + .../contrib/arch/x86/include/asm/numa_64.h | 43 + .../contrib/arch/x86/include/asm/numaq.h | 169 ++ .../contrib/arch/x86/include/asm/numaq/apic.h | 142 ++ .../contrib/arch/x86/include/asm/numaq/apicdef.h | 14 + .../contrib/arch/x86/include/asm/numaq/ipi.h | 22 + .../contrib/arch/x86/include/asm/numaq/mpparse.h | 6 + .../contrib/arch/x86/include/asm/numaq/wakecpu.h | 45 + libdde-linux26/contrib/arch/x86/include/asm/olpc.h | 132 ++ libdde-linux26/contrib/arch/x86/include/asm/page.h | 208 +++ .../contrib/arch/x86/include/asm/page_32.h | 136 ++ .../contrib/arch/x86/include/asm/page_64.h | 105 ++ .../contrib/arch/x86/include/asm/param.h | 22 + .../contrib/arch/x86/include/asm/paravirt.h | 1638 ++++++++++++++++++++ .../contrib/arch/x86/include/asm/parport.h | 10 + libdde-linux26/contrib/arch/x86/include/asm/pat.h | 22 + .../contrib/arch/x86/include/asm/pci-direct.h | 21 + libdde-linux26/contrib/arch/x86/include/asm/pci.h | 124 ++ .../contrib/arch/x86/include/asm/pci_32.h | 34 + .../contrib/arch/x86/include/asm/pci_64.h | 51 + .../contrib/arch/x86/include/asm/pci_x86.h | 165 ++ libdde-linux26/contrib/arch/x86/include/asm/pda.h | 137 ++ .../contrib/arch/x86/include/asm/percpu.h | 218 +++ .../contrib/arch/x86/include/asm/pgalloc.h | 115 ++ .../arch/x86/include/asm/pgtable-2level-defs.h | 20 + .../contrib/arch/x86/include/asm/pgtable-2level.h | 111 ++ .../arch/x86/include/asm/pgtable-3level-defs.h | 28 + .../contrib/arch/x86/include/asm/pgtable-3level.h | 176 +++ .../contrib/arch/x86/include/asm/pgtable.h | 611 ++++++++ .../contrib/arch/x86/include/asm/pgtable_32.h | 182 +++ .../contrib/arch/x86/include/asm/pgtable_64.h | 291 ++++ libdde-linux26/contrib/arch/x86/include/asm/poll.h | 1 + .../contrib/arch/x86/include/asm/posix_types.h | 13 + .../contrib/arch/x86/include/asm/posix_types_32.h | 85 + .../contrib/arch/x86/include/asm/posix_types_64.h | 119 ++ .../contrib/arch/x86/include/asm/prctl.h | 13 + .../contrib/arch/x86/include/asm/processor-cyrix.h | 38 + .../contrib/arch/x86/include/asm/processor-flags.h | 100 ++ .../contrib/arch/x86/include/asm/processor.h | 953 ++++++++++++ .../contrib/arch/x86/include/asm/proto.h | 32 + .../contrib/arch/x86/include/asm/ptrace-abi.h | 145 ++ .../contrib/arch/x86/include/asm/ptrace.h | 249 +++ .../contrib/arch/x86/include/asm/pvclock-abi.h | 42 + .../contrib/arch/x86/include/asm/pvclock.h | 14 + .../contrib/arch/x86/include/asm/reboot.h | 26 + .../contrib/arch/x86/include/asm/reboot_fixups.h | 6 + .../arch/x86/include/asm/required-features.h | 82 + .../contrib/arch/x86/include/asm/resource.h | 1 + .../contrib/arch/x86/include/asm/resume-trace.h | 21 + libdde-linux26/contrib/arch/x86/include/asm/rio.h | 63 + libdde-linux26/contrib/arch/x86/include/asm/rtc.h | 1 + .../contrib/arch/x86/include/asm/rwlock.h | 8 + .../contrib/arch/x86/include/asm/rwsem.h | 265 ++++ .../contrib/arch/x86/include/asm/scatterlist.h | 33 + .../contrib/arch/x86/include/asm/seccomp.h | 5 + .../contrib/arch/x86/include/asm/seccomp_32.h | 11 + .../contrib/arch/x86/include/asm/seccomp_64.h | 17 + .../contrib/arch/x86/include/asm/sections.h | 1 + .../contrib/arch/x86/include/asm/segment.h | 209 +++ .../contrib/arch/x86/include/asm/sembuf.h | 24 + .../contrib/arch/x86/include/asm/serial.h | 29 + .../contrib/arch/x86/include/asm/setup.h | 112 ++ .../contrib/arch/x86/include/asm/shmbuf.h | 51 + .../contrib/arch/x86/include/asm/shmparam.h | 6 + .../contrib/arch/x86/include/asm/sigcontext.h | 284 ++++ .../contrib/arch/x86/include/asm/sigcontext32.h | 77 + .../contrib/arch/x86/include/asm/sigframe.h | 70 + .../contrib/arch/x86/include/asm/siginfo.h | 10 + .../contrib/arch/x86/include/asm/signal.h | 264 ++++ libdde-linux26/contrib/arch/x86/include/asm/smp.h | 261 ++++ .../contrib/arch/x86/include/asm/socket.h | 57 + .../contrib/arch/x86/include/asm/sockios.h | 13 + .../contrib/arch/x86/include/asm/sparsemem.h | 34 + .../contrib/arch/x86/include/asm/spinlock.h | 365 +++++ .../contrib/arch/x86/include/asm/spinlock_types.h | 20 + libdde-linux26/contrib/arch/x86/include/asm/srat.h | 39 + .../contrib/arch/x86/include/asm/stacktrace.h | 21 + libdde-linux26/contrib/arch/x86/include/asm/stat.h | 114 ++ .../contrib/arch/x86/include/asm/statfs.h | 12 + .../contrib/arch/x86/include/asm/string.h | 5 + .../contrib/arch/x86/include/asm/string_32.h | 326 ++++ .../contrib/arch/x86/include/asm/string_64.h | 60 + .../contrib/arch/x86/include/asm/summit/apic.h | 202 +++ .../contrib/arch/x86/include/asm/summit/apicdef.h | 13 + .../contrib/arch/x86/include/asm/summit/ipi.h | 26 + .../contrib/arch/x86/include/asm/summit/mpparse.h | 109 ++ .../contrib/arch/x86/include/asm/suspend.h | 5 + .../contrib/arch/x86/include/asm/suspend_32.h | 51 + .../contrib/arch/x86/include/asm/suspend_64.h | 52 + libdde-linux26/contrib/arch/x86/include/asm/svm.h | 328 ++++ libdde-linux26/contrib/arch/x86/include/asm/swab.h | 61 + .../contrib/arch/x86/include/asm/swiotlb.h | 22 + .../contrib/arch/x86/include/asm/sync_bitops.h | 130 ++ .../contrib/arch/x86/include/asm/sys_ia32.h | 101 ++ .../contrib/arch/x86/include/asm/syscall.h | 213 +++ .../contrib/arch/x86/include/asm/syscalls.h | 93 ++ .../contrib/arch/x86/include/asm/system.h | 427 +++++ .../contrib/arch/x86/include/asm/system_64.h | 22 + libdde-linux26/contrib/arch/x86/include/asm/tce.h | 48 + .../contrib/arch/x86/include/asm/termbits.h | 198 +++ .../contrib/arch/x86/include/asm/termios.h | 113 ++ .../contrib/arch/x86/include/asm/therm_throt.h | 9 + .../contrib/arch/x86/include/asm/thread_info.h | 263 ++++ libdde-linux26/contrib/arch/x86/include/asm/time.h | 63 + .../contrib/arch/x86/include/asm/timer.h | 66 + .../contrib/arch/x86/include/asm/timex.h | 14 + libdde-linux26/contrib/arch/x86/include/asm/tlb.h | 11 + .../contrib/arch/x86/include/asm/tlbflush.h | 178 +++ .../contrib/arch/x86/include/asm/topology.h | 273 ++++ .../contrib/arch/x86/include/asm/trampoline.h | 28 + .../contrib/arch/x86/include/asm/traps.h | 88 ++ libdde-linux26/contrib/arch/x86/include/asm/tsc.h | 62 + .../contrib/arch/x86/include/asm/types.h | 36 + .../contrib/arch/x86/include/asm/uaccess.h | 456 ++++++ .../contrib/arch/x86/include/asm/uaccess_32.h | 218 +++ .../contrib/arch/x86/include/asm/uaccess_64.h | 208 +++ .../contrib/arch/x86/include/asm/ucontext.h | 18 + .../contrib/arch/x86/include/asm/unaligned.h | 14 + .../contrib/arch/x86/include/asm/unistd.h | 13 + .../contrib/arch/x86/include/asm/unistd_32.h | 379 +++++ .../contrib/arch/x86/include/asm/unistd_64.h | 693 +++++++++ libdde-linux26/contrib/arch/x86/include/asm/user.h | 5 + .../contrib/arch/x86/include/asm/user32.h | 70 + .../contrib/arch/x86/include/asm/user_32.h | 131 ++ .../contrib/arch/x86/include/asm/user_64.h | 137 ++ .../contrib/arch/x86/include/asm/uv/bios.h | 120 ++ .../contrib/arch/x86/include/asm/uv/uv_bau.h | 332 ++++ .../contrib/arch/x86/include/asm/uv/uv_hub.h | 404 +++++ .../contrib/arch/x86/include/asm/uv/uv_irq.h | 36 + .../contrib/arch/x86/include/asm/uv/uv_mmrs.h | 1295 ++++++++++++++++ libdde-linux26/contrib/arch/x86/include/asm/vdso.h | 47 + libdde-linux26/contrib/arch/x86/include/asm/vga.h | 20 + .../contrib/arch/x86/include/asm/vgtod.h | 29 + libdde-linux26/contrib/arch/x86/include/asm/vic.h | 61 + .../contrib/arch/x86/include/asm/virtext.h | 132 ++ .../contrib/arch/x86/include/asm/visws/cobalt.h | 125 ++ .../contrib/arch/x86/include/asm/visws/lithium.h | 53 + .../contrib/arch/x86/include/asm/visws/piix4.h | 107 ++ .../contrib/arch/x86/include/asm/visws/sgivw.h | 5 + libdde-linux26/contrib/arch/x86/include/asm/vm86.h | 208 +++ libdde-linux26/contrib/arch/x86/include/asm/vmi.h | 269 ++++ .../contrib/arch/x86/include/asm/vmi_time.h | 98 ++ .../contrib/arch/x86/include/asm/vmware.h | 27 + libdde-linux26/contrib/arch/x86/include/asm/vmx.h | 382 +++++ .../contrib/arch/x86/include/asm/voyager.h | 529 +++++++ .../contrib/arch/x86/include/asm/vsyscall.h | 44 + libdde-linux26/contrib/arch/x86/include/asm/xcr.h | 49 + .../contrib/arch/x86/include/asm/xen/events.h | 24 + .../contrib/arch/x86/include/asm/xen/grant_table.h | 7 + .../contrib/arch/x86/include/asm/xen/hypercall.h | 533 +++++++ .../contrib/arch/x86/include/asm/xen/hypervisor.h | 59 + .../contrib/arch/x86/include/asm/xen/interface.h | 175 +++ .../arch/x86/include/asm/xen/interface_32.h | 97 ++ .../arch/x86/include/asm/xen/interface_64.h | 159 ++ .../contrib/arch/x86/include/asm/xen/page.h | 170 ++ libdde-linux26/contrib/arch/x86/include/asm/xor.h | 5 + .../contrib/arch/x86/include/asm/xor_32.h | 888 +++++++++++ .../contrib/arch/x86/include/asm/xor_64.h | 361 +++++ .../contrib/arch/x86/include/asm/xsave.h | 118 ++ libdde-linux26/contrib/arch/x86/kernel/pci-dma.c | 299 ++++ libdde-linux26/contrib/arch/x86/kernel/pci-nommu.c | 96 ++ libdde-linux26/contrib/arch/x86/lib/checksum_32.S | 546 +++++++ 364 files changed, 43464 insertions(+) create mode 100644 libdde-linux26/contrib/arch/arm/kernel/ptrace.h create mode 100644 libdde-linux26/contrib/arch/arm/kernel/signal.h create mode 100644 libdde-linux26/contrib/arch/arm/kernel/traps.c create mode 100644 libdde-linux26/contrib/arch/arm/lib/bitops.h create mode 100644 libdde-linux26/contrib/arch/arm/lib/changebit.S create mode 100644 libdde-linux26/contrib/arch/arm/lib/clearbit.S create mode 100644 libdde-linux26/contrib/arch/arm/lib/div64.S create mode 100644 libdde-linux26/contrib/arch/arm/lib/findbit.S create mode 100644 libdde-linux26/contrib/arch/arm/lib/memzero.S create mode 100644 libdde-linux26/contrib/arch/arm/lib/setbit.S create mode 100644 libdde-linux26/contrib/arch/arm/lib/testchangebit.S create mode 100644 libdde-linux26/contrib/arch/arm/lib/testclearbit.S create mode 100644 libdde-linux26/contrib/arch/arm/lib/testsetbit.S create mode 100644 libdde-linux26/contrib/arch/arm/mach-realview/clock.c create mode 100644 libdde-linux26/contrib/arch/arm/mach-realview/clock.h create mode 100644 libdde-linux26/contrib/arch/arm/mach-realview/core.h create mode 100644 libdde-linux26/contrib/arch/arm/mach-realview/realview_eb.c create mode 100644 libdde-linux26/contrib/arch/x86/include/Makefile create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/Kbuild create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/a.out-core.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/a.out.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/acpi.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/agp.h create mode 100644 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libdde-linux26/contrib/arch/x86/include/asm/bigsmp/apicdef.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/bigsmp/ipi.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/bios_ebda.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/bitops.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/boot.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/bootparam.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/bug.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/bugs.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/byteorder.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/cache.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/cacheflush.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/calgary.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/calling.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/checksum.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/checksum_32.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/checksum_64.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/cmpxchg.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/cmpxchg_32.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/cmpxchg_64.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/compat.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/cpu.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/cpufeature.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/cputime.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/current.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/debugreg.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/delay.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/desc.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/desc_defs.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/device.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/div64.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/dma-mapping.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/dma.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/dmi.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/ds.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/dwarf2.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/e820.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/edac.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/efi.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/elf.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/emergency-restart.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/errno.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/es7000/apic.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/es7000/apicdef.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/es7000/ipi.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/es7000/mpparse.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/es7000/wakecpu.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/fb.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/fcntl.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/fixmap.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/fixmap_32.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/fixmap_64.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/floppy.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/frame.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/ftrace.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/futex.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/gart.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/genapic.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/genapic_32.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/genapic_64.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/geode.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/gpio.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/hardirq.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/hardirq_32.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/hardirq_64.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/highmem.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/hpet.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/hugetlb.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/hw_irq.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/hypertransport.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/hypervisor.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/i387.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/i8253.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/i8259.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/ia32.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/ia32_unistd.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/idle.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/intel_arch_perfmon.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/io.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/io_32.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/io_64.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/io_apic.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/ioctl.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/ioctls.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/iomap.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/iommu.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/ipcbuf.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/ipi.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/irq.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/irq_regs.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/irq_regs_32.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/irq_regs_64.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/irq_remapping.h create mode 100644 libdde-linux26/contrib/arch/x86/include/asm/irq_vectors.h create mode 100644 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libdde-linux26/contrib/arch/x86/kernel/pci-nommu.c create mode 100644 libdde-linux26/contrib/arch/x86/lib/checksum_32.S (limited to 'libdde-linux26/contrib/arch') diff --git a/libdde-linux26/contrib/arch/arm/kernel/ptrace.h b/libdde-linux26/contrib/arch/arm/kernel/ptrace.h new file mode 100644 index 00000000..def3b618 --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/kernel/ptrace.h @@ -0,0 +1,51 @@ +/* + * linux/arch/arm/kernel/ptrace.h + * + * Copyright (C) 2000-2003 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include + +extern void ptrace_cancel_bpt(struct task_struct *); +extern void ptrace_set_bpt(struct task_struct *); +extern void ptrace_break(struct task_struct *, struct pt_regs *); + +/* + * make sure single-step breakpoint is gone. + */ +static inline void single_step_disable(struct task_struct *task) +{ + task->ptrace &= ~PT_SINGLESTEP; + ptrace_cancel_bpt(task); +} + +static inline void single_step_enable(struct task_struct *task) +{ + task->ptrace |= PT_SINGLESTEP; +} + +/* + * Send SIGTRAP if we're single-stepping + */ +static inline void single_step_trap(struct task_struct *task) +{ + if (task->ptrace & PT_SINGLESTEP) { + ptrace_cancel_bpt(task); + send_sig(SIGTRAP, task, 1); + } +} + +static inline void single_step_clear(struct task_struct *task) +{ + if (task->ptrace & PT_SINGLESTEP) + ptrace_cancel_bpt(task); +} + +static inline void single_step_set(struct task_struct *task) +{ + if (task->ptrace & PT_SINGLESTEP) + ptrace_set_bpt(task); +} diff --git a/libdde-linux26/contrib/arch/arm/kernel/signal.h b/libdde-linux26/contrib/arch/arm/kernel/signal.h new file mode 100644 index 00000000..27beece1 --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/kernel/signal.h @@ -0,0 +1,12 @@ +/* + * linux/arch/arm/kernel/signal.h + * + * Copyright (C) 2005 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#define KERN_SIGRETURN_CODE (CONFIG_VECTORS_BASE + 0x00000500) + +extern const unsigned long sigreturn_codes[7]; diff --git a/libdde-linux26/contrib/arch/arm/kernel/traps.c b/libdde-linux26/contrib/arch/arm/kernel/traps.c new file mode 100644 index 00000000..79abc4dd --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/kernel/traps.c @@ -0,0 +1,734 @@ +/* + * linux/arch/arm/kernel/traps.c + * + * Copyright (C) 1995-2002 Russell King + * Fragments that appear the same as linux/arch/i386/kernel/traps.c (C) Linus Torvalds + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * 'traps.c' handles hardware exceptions after we have saved some state in + * 'linux/arch/arm/lib/traps.S'. Mostly a debugging aid, but will probably + * kill the offending process. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "ptrace.h" +#include "signal.h" + +static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" }; + +#ifdef CONFIG_DEBUG_USER +unsigned int user_debug; + +static int __init user_debug_setup(char *str) +{ + get_option(&str, &user_debug); + return 1; +} +__setup("user_debug=", user_debug_setup); +#endif + +static void dump_mem(const char *str, unsigned long bottom, unsigned long top); + +void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame) +{ +#ifdef CONFIG_KALLSYMS + printk("[<%08lx>] ", where); + print_symbol("(%s) ", where); + printk("from [<%08lx>] ", from); + print_symbol("(%s)\n", from); +#else + printk("Function entered at [<%08lx>] from [<%08lx>]\n", where, from); +#endif + + if (in_exception_text(where)) + dump_mem("Exception stack", frame + 4, frame + 4 + sizeof(struct pt_regs)); +} + +/* + * Stack pointers should always be within the kernels view of + * physical memory. If it is not there, then we can't dump + * out any information relating to the stack. + */ +static int verify_stack(unsigned long sp) +{ + if (sp < PAGE_OFFSET || + (sp > (unsigned long)high_memory && high_memory != NULL)) + return -EFAULT; + + return 0; +} + +/* + * Dump out the contents of some memory nicely... + */ +static void dump_mem(const char *str, unsigned long bottom, unsigned long top) +{ + unsigned long p = bottom & ~31; + mm_segment_t fs; + int i; + + /* + * We need to switch to kernel mode so that we can use __get_user + * to safely read from kernel space. Note that we now dump the + * code first, just in case the backtrace kills us. + */ + fs = get_fs(); + set_fs(KERNEL_DS); + + printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); + + for (p = bottom & ~31; p < top;) { + printk("%04lx: ", p & 0xffff); + + for (i = 0; i < 8; i++, p += 4) { + unsigned int val; + + if (p < bottom || p >= top) + printk(" "); + else { + __get_user(val, (unsigned long *)p); + printk("%08x ", val); + } + } + printk ("\n"); + } + + set_fs(fs); +} + +static void dump_instr(struct pt_regs *regs) +{ + unsigned long addr = instruction_pointer(regs); + const int thumb = thumb_mode(regs); + const int width = thumb ? 4 : 8; + mm_segment_t fs; + int i; + + /* + * We need to switch to kernel mode so that we can use __get_user + * to safely read from kernel space. Note that we now dump the + * code first, just in case the backtrace kills us. + */ + fs = get_fs(); + set_fs(KERNEL_DS); + + printk("Code: "); + for (i = -4; i < 1; i++) { + unsigned int val, bad; + + if (thumb) + bad = __get_user(val, &((u16 *)addr)[i]); + else + bad = __get_user(val, &((u32 *)addr)[i]); + + if (!bad) + printk(i == 0 ? "(%0*x) " : "%0*x ", width, val); + else { + printk("bad PC value."); + break; + } + } + printk("\n"); + + set_fs(fs); +} + +static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) +{ + unsigned int fp; + int ok = 1; + + printk("Backtrace: "); + fp = regs->ARM_fp; + if (!fp) { + printk("no frame pointer"); + ok = 0; + } else if (verify_stack(fp)) { + printk("invalid frame pointer 0x%08x", fp); + ok = 0; + } else if (fp < (unsigned long)end_of_stack(tsk)) + printk("frame pointer underflow"); + printk("\n"); + + if (ok) + c_backtrace(fp, processor_mode(regs)); +} + +void dump_stack(void) +{ + __backtrace(); +} + +EXPORT_SYMBOL(dump_stack); + +void show_stack(struct task_struct *tsk, unsigned long *sp) +{ + unsigned long fp; + + if (!tsk) + tsk = current; + + if (tsk != current) + fp = thread_saved_fp(tsk); + else + asm("mov %0, fp" : "=r" (fp) : : "cc"); + + c_backtrace(fp, 0x10); + barrier(); +} + +#ifdef CONFIG_PREEMPT +#define S_PREEMPT " PREEMPT" +#else +#define S_PREEMPT "" +#endif +#ifdef CONFIG_SMP +#define S_SMP " SMP" +#else +#define S_SMP "" +#endif + +static void __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs) +{ + struct task_struct *tsk = thread->task; + static int die_counter; + + printk("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", + str, err, ++die_counter); + print_modules(); + __show_regs(regs); + printk("Process %s (pid: %d, stack limit = 0x%p)\n", + tsk->comm, task_pid_nr(tsk), thread + 1); + + if (!user_mode(regs) || in_interrupt()) { + dump_mem("Stack: ", regs->ARM_sp, + THREAD_SIZE + (unsigned long)task_stack_page(tsk)); + dump_backtrace(regs, tsk); + dump_instr(regs); + } +} + +DEFINE_SPINLOCK(die_lock); + +/* + * This function is protected against re-entrancy. + */ +NORET_TYPE void die(const char *str, struct pt_regs *regs, int err) +{ + struct thread_info *thread = current_thread_info(); + + oops_enter(); + + console_verbose(); + spin_lock_irq(&die_lock); + bust_spinlocks(1); + __die(str, err, thread, regs); + bust_spinlocks(0); + add_taint(TAINT_DIE); + spin_unlock_irq(&die_lock); + + if (in_interrupt()) + panic("Fatal exception in interrupt"); + + if (panic_on_oops) + panic("Fatal exception"); + + oops_exit(); + do_exit(SIGSEGV); +} + +void arm_notify_die(const char *str, struct pt_regs *regs, + struct siginfo *info, unsigned long err, unsigned long trap) +{ + if (user_mode(regs)) { + current->thread.error_code = err; + current->thread.trap_no = trap; + + force_sig_info(info->si_signo, info, current); + } else { + die(str, regs, err); + } +} + +static LIST_HEAD(undef_hook); +static DEFINE_SPINLOCK(undef_lock); + +void register_undef_hook(struct undef_hook *hook) +{ + unsigned long flags; + + spin_lock_irqsave(&undef_lock, flags); + list_add(&hook->node, &undef_hook); + spin_unlock_irqrestore(&undef_lock, flags); +} + +void unregister_undef_hook(struct undef_hook *hook) +{ + unsigned long flags; + + spin_lock_irqsave(&undef_lock, flags); + list_del(&hook->node); + spin_unlock_irqrestore(&undef_lock, flags); +} + +static int call_undef_hook(struct pt_regs *regs, unsigned int instr) +{ + struct undef_hook *hook; + unsigned long flags; + int (*fn)(struct pt_regs *regs, unsigned int instr) = NULL; + + spin_lock_irqsave(&undef_lock, flags); + list_for_each_entry(hook, &undef_hook, node) + if ((instr & hook->instr_mask) == hook->instr_val && + (regs->ARM_cpsr & hook->cpsr_mask) == hook->cpsr_val) + fn = hook->fn; + spin_unlock_irqrestore(&undef_lock, flags); + + return fn ? fn(regs, instr) : 1; +} + +asmlinkage void __exception do_undefinstr(struct pt_regs *regs) +{ + unsigned int correction = thumb_mode(regs) ? 2 : 4; + unsigned int instr; + siginfo_t info; + void __user *pc; + + /* + * According to the ARM ARM, PC is 2 or 4 bytes ahead, + * depending whether we're in Thumb mode or not. + * Correct this offset. + */ + regs->ARM_pc -= correction; + + pc = (void __user *)instruction_pointer(regs); + + if (processor_mode(regs) == SVC_MODE) { + instr = *(u32 *) pc; + } else if (thumb_mode(regs)) { + get_user(instr, (u16 __user *)pc); + } else { + get_user(instr, (u32 __user *)pc); + } + + if (call_undef_hook(regs, instr) == 0) + return; + +#ifdef CONFIG_DEBUG_USER + if (user_debug & UDBG_UNDEFINED) { + printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n", + current->comm, task_pid_nr(current), pc); + dump_instr(regs); + } +#endif + + info.si_signo = SIGILL; + info.si_errno = 0; + info.si_code = ILL_ILLOPC; + info.si_addr = pc; + + arm_notify_die("Oops - undefined instruction", regs, &info, 0, 6); +} + +asmlinkage void do_unexp_fiq (struct pt_regs *regs) +{ + printk("Hmm. Unexpected FIQ received, but trying to continue\n"); + printk("You may have a hardware problem...\n"); +} + +/* + * bad_mode handles the impossible case in the vectors. If you see one of + * these, then it's extremely serious, and could mean you have buggy hardware. + * It never returns, and never tries to sync. We hope that we can at least + * dump out some state information... + */ +asmlinkage void bad_mode(struct pt_regs *regs, int reason) +{ + console_verbose(); + + printk(KERN_CRIT "Bad mode in %s handler detected\n", handler[reason]); + + die("Oops - bad mode", regs, 0); + local_irq_disable(); + panic("bad mode"); +} + +static int bad_syscall(int n, struct pt_regs *regs) +{ + struct thread_info *thread = current_thread_info(); + siginfo_t info; + + if (current->personality != PER_LINUX && + current->personality != PER_LINUX_32BIT && + thread->exec_domain->handler) { + thread->exec_domain->handler(n, regs); + return regs->ARM_r0; + } + +#ifdef CONFIG_DEBUG_USER + if (user_debug & UDBG_SYSCALL) { + printk(KERN_ERR "[%d] %s: obsolete system call %08x.\n", + task_pid_nr(current), current->comm, n); + dump_instr(regs); + } +#endif + + info.si_signo = SIGILL; + info.si_errno = 0; + info.si_code = ILL_ILLTRP; + info.si_addr = (void __user *)instruction_pointer(regs) - + (thumb_mode(regs) ? 2 : 4); + + arm_notify_die("Oops - bad syscall", regs, &info, n, 0); + + return regs->ARM_r0; +} + +static inline void +do_cache_op(unsigned long start, unsigned long end, int flags) +{ + struct vm_area_struct *vma; + + if (end < start || flags) + return; + + vma = find_vma(current->active_mm, start); + if (vma && vma->vm_start < end) { + if (start < vma->vm_start) + start = vma->vm_start; + if (end > vma->vm_end) + end = vma->vm_end; + + flush_cache_user_range(vma, start, end); + } +} + +/* + * Handle all unrecognised system calls. + * 0x9f0000 - 0x9fffff are some more esoteric system calls + */ +#define NR(x) ((__ARM_NR_##x) - __ARM_NR_BASE) +asmlinkage int arm_syscall(int no, struct pt_regs *regs) +{ + struct thread_info *thread = current_thread_info(); + siginfo_t info; + + if ((no >> 16) != (__ARM_NR_BASE>> 16)) + return bad_syscall(no, regs); + + switch (no & 0xffff) { + case 0: /* branch through 0 */ + info.si_signo = SIGSEGV; + info.si_errno = 0; + info.si_code = SEGV_MAPERR; + info.si_addr = NULL; + + arm_notify_die("branch through zero", regs, &info, 0, 0); + return 0; + + case NR(breakpoint): /* SWI BREAK_POINT */ + regs->ARM_pc -= thumb_mode(regs) ? 2 : 4; + ptrace_break(current, regs); + return regs->ARM_r0; + + /* + * Flush a region from virtual address 'r0' to virtual address 'r1' + * _exclusive_. There is no alignment requirement on either address; + * user space does not need to know the hardware cache layout. + * + * r2 contains flags. It should ALWAYS be passed as ZERO until it + * is defined to be something else. For now we ignore it, but may + * the fires of hell burn in your belly if you break this rule. ;) + * + * (at a later date, we may want to allow this call to not flush + * various aspects of the cache. Passing '0' will guarantee that + * everything necessary gets flushed to maintain consistency in + * the specified region). + */ + case NR(cacheflush): + do_cache_op(regs->ARM_r0, regs->ARM_r1, regs->ARM_r2); + return 0; + + case NR(usr26): + if (!(elf_hwcap & HWCAP_26BIT)) + break; + regs->ARM_cpsr &= ~MODE32_BIT; + return regs->ARM_r0; + + case NR(usr32): + if (!(elf_hwcap & HWCAP_26BIT)) + break; + regs->ARM_cpsr |= MODE32_BIT; + return regs->ARM_r0; + + case NR(set_tls): + thread->tp_value = regs->ARM_r0; +#if defined(CONFIG_HAS_TLS_REG) + asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) ); +#elif !defined(CONFIG_TLS_REG_EMUL) + /* + * User space must never try to access this directly. + * Expect your app to break eventually if you do so. + * The user helper at 0xffff0fe0 must be used instead. + * (see entry-armv.S for details) + */ + *((unsigned int *)0xffff0ff0) = regs->ARM_r0; +#endif + return 0; + +#ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG + /* + * Atomically store r1 in *r2 if *r2 is equal to r0 for user space. + * Return zero in r0 if *MEM was changed or non-zero if no exchange + * happened. Also set the user C flag accordingly. + * If access permissions have to be fixed up then non-zero is + * returned and the operation has to be re-attempted. + * + * *NOTE*: This is a ghost syscall private to the kernel. Only the + * __kuser_cmpxchg code in entry-armv.S should be aware of its + * existence. Don't ever use this from user code. + */ + case 0xfff0: + for (;;) { + extern void do_DataAbort(unsigned long addr, unsigned int fsr, + struct pt_regs *regs); + unsigned long val; + unsigned long addr = regs->ARM_r2; + struct mm_struct *mm = current->mm; + pgd_t *pgd; pmd_t *pmd; pte_t *pte; + spinlock_t *ptl; + + regs->ARM_cpsr &= ~PSR_C_BIT; + down_read(&mm->mmap_sem); + pgd = pgd_offset(mm, addr); + if (!pgd_present(*pgd)) + goto bad_access; + pmd = pmd_offset(pgd, addr); + if (!pmd_present(*pmd)) + goto bad_access; + pte = pte_offset_map_lock(mm, pmd, addr, &ptl); + if (!pte_present(*pte) || !pte_dirty(*pte)) { + pte_unmap_unlock(pte, ptl); + goto bad_access; + } + val = *(unsigned long *)addr; + val -= regs->ARM_r0; + if (val == 0) { + *(unsigned long *)addr = regs->ARM_r1; + regs->ARM_cpsr |= PSR_C_BIT; + } + pte_unmap_unlock(pte, ptl); + up_read(&mm->mmap_sem); + return val; + + bad_access: + up_read(&mm->mmap_sem); + /* simulate a write access fault */ + do_DataAbort(addr, 15 + (1 << 11), regs); + } +#endif + + default: + /* Calls 9f00xx..9f07ff are defined to return -ENOSYS + if not implemented, rather than raising SIGILL. This + way the calling program can gracefully determine whether + a feature is supported. */ + if (no <= 0x7ff) + return -ENOSYS; + break; + } +#ifdef CONFIG_DEBUG_USER + /* + * experience shows that these seem to indicate that + * something catastrophic has happened + */ + if (user_debug & UDBG_SYSCALL) { + printk("[%d] %s: arm syscall %d\n", + task_pid_nr(current), current->comm, no); + dump_instr(regs); + if (user_mode(regs)) { + __show_regs(regs); + c_backtrace(regs->ARM_fp, processor_mode(regs)); + } + } +#endif + info.si_signo = SIGILL; + info.si_errno = 0; + info.si_code = ILL_ILLTRP; + info.si_addr = (void __user *)instruction_pointer(regs) - + (thumb_mode(regs) ? 2 : 4); + + arm_notify_die("Oops - bad syscall(2)", regs, &info, no, 0); + return 0; +} + +#ifdef CONFIG_TLS_REG_EMUL + +/* + * We might be running on an ARMv6+ processor which should have the TLS + * register but for some reason we can't use it, or maybe an SMP system + * using a pre-ARMv6 processor (there are apparently a few prototypes like + * that in existence) and therefore access to that register must be + * emulated. + */ + +static int get_tp_trap(struct pt_regs *regs, unsigned int instr) +{ + int reg = (instr >> 12) & 15; + if (reg == 15) + return 1; + regs->uregs[reg] = current_thread_info()->tp_value; + regs->ARM_pc += 4; + return 0; +} + +static struct undef_hook arm_mrc_hook = { + .instr_mask = 0x0fff0fff, + .instr_val = 0x0e1d0f70, + .cpsr_mask = PSR_T_BIT, + .cpsr_val = 0, + .fn = get_tp_trap, +}; + +static int __init arm_mrc_hook_init(void) +{ + register_undef_hook(&arm_mrc_hook); + return 0; +} + +late_initcall(arm_mrc_hook_init); + +#endif + +void __bad_xchg(volatile void *ptr, int size) +{ + printk("xchg: bad data size: pc 0x%p, ptr 0x%p, size %d\n", + __builtin_return_address(0), ptr, size); + BUG(); +} +EXPORT_SYMBOL(__bad_xchg); + +/* + * A data abort trap was taken, but we did not handle the instruction. + * Try to abort the user program, or panic if it was the kernel. + */ +asmlinkage void +baddataabort(int code, unsigned long instr, struct pt_regs *regs) +{ + unsigned long addr = instruction_pointer(regs); + siginfo_t info; + +#ifdef CONFIG_DEBUG_USER + if (user_debug & UDBG_BADABORT) { + printk(KERN_ERR "[%d] %s: bad data abort: code %d instr 0x%08lx\n", + task_pid_nr(current), current->comm, code, instr); + dump_instr(regs); + show_pte(current->mm, addr); + } +#endif + + info.si_signo = SIGILL; + info.si_errno = 0; + info.si_code = ILL_ILLOPC; + info.si_addr = (void __user *)addr; + + arm_notify_die("unknown data abort code", regs, &info, instr, 0); +} + +void __attribute__((noreturn)) __bug(const char *file, int line) +{ + printk(KERN_CRIT"kernel BUG at %s:%d!\n", file, line); + *(int *)0 = 0; + + /* Avoid "noreturn function does return" */ + for (;;); +} +EXPORT_SYMBOL(__bug); + +void __readwrite_bug(const char *fn) +{ + printk("%s called, but not implemented\n", fn); + BUG(); +} +EXPORT_SYMBOL(__readwrite_bug); + +void __pte_error(const char *file, int line, unsigned long val) +{ + printk("%s:%d: bad pte %08lx.\n", file, line, val); +} + +void __pmd_error(const char *file, int line, unsigned long val) +{ + printk("%s:%d: bad pmd %08lx.\n", file, line, val); +} + +void __pgd_error(const char *file, int line, unsigned long val) +{ + printk("%s:%d: bad pgd %08lx.\n", file, line, val); +} + +asmlinkage void __div0(void) +{ + printk("Division by zero in kernel.\n"); + dump_stack(); +} +EXPORT_SYMBOL(__div0); + +void abort(void) +{ + BUG(); + + /* if that doesn't kill us, halt */ + panic("Oops failed to kill thread"); +} +EXPORT_SYMBOL(abort); + +void __init trap_init(void) +{ + return; +} + +void __init early_trap_init(void) +{ + unsigned long vectors = CONFIG_VECTORS_BASE; + extern char __stubs_start[], __stubs_end[]; + extern char __vectors_start[], __vectors_end[]; + extern char __kuser_helper_start[], __kuser_helper_end[]; + int kuser_sz = __kuser_helper_end - __kuser_helper_start; + + /* + * Copy the vectors, stubs and kuser helpers (in entry-armv.S) + * into the vector page, mapped at 0xffff0000, and ensure these + * are visible to the instruction stream. + */ + memcpy((void *)vectors, __vectors_start, __vectors_end - __vectors_start); + memcpy((void *)vectors + 0x200, __stubs_start, __stubs_end - __stubs_start); + memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz); + + /* + * Copy signal return handlers into the vector page, and + * set sigreturn to be a pointer to these. + */ + memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes, + sizeof(sigreturn_codes)); + + flush_icache_range(vectors, vectors + PAGE_SIZE); + modify_domain(DOMAIN_USER, DOMAIN_CLIENT); +} diff --git a/libdde-linux26/contrib/arch/arm/lib/bitops.h b/libdde-linux26/contrib/arch/arm/lib/bitops.h new file mode 100644 index 00000000..2e787d40 --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/lib/bitops.h @@ -0,0 +1,65 @@ + +#if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_CPU_32v6K) + .macro bitop, instr + mov r2, #1 + and r3, r0, #7 @ Get bit offset + add r1, r1, r0, lsr #3 @ Get byte offset + mov r3, r2, lsl r3 +1: ldrexb r2, [r1] + \instr r2, r2, r3 + strexb r0, r2, [r1] + cmp r0, #0 + bne 1b + mov pc, lr + .endm + + .macro testop, instr, store + and r3, r0, #7 @ Get bit offset + mov r2, #1 + add r1, r1, r0, lsr #3 @ Get byte offset + mov r3, r2, lsl r3 @ create mask +1: ldrexb r2, [r1] + ands r0, r2, r3 @ save old value of bit + \instr r2, r2, r3 @ toggle bit + strexb ip, r2, [r1] + cmp ip, #0 + bne 1b + cmp r0, #0 + movne r0, #1 +2: mov pc, lr + .endm +#else + .macro bitop, instr + and r2, r0, #7 + mov r3, #1 + mov r3, r3, lsl r2 + save_and_disable_irqs ip + ldrb r2, [r1, r0, lsr #3] + \instr r2, r2, r3 + strb r2, [r1, r0, lsr #3] + restore_irqs ip + mov pc, lr + .endm + +/** + * testop - implement a test_and_xxx_bit operation. + * @instr: operational instruction + * @store: store instruction + * + * Note: we can trivially conditionalise the store instruction + * to avoid dirtying the data cache. + */ + .macro testop, instr, store + add r1, r1, r0, lsr #3 + and r3, r0, #7 + mov r0, #1 + save_and_disable_irqs ip + ldrb r2, [r1] + tst r2, r0, lsl r3 + \instr r2, r2, r0, lsl r3 + \store r2, [r1] + restore_irqs ip + moveq r0, #0 + mov pc, lr + .endm +#endif diff --git a/libdde-linux26/contrib/arch/arm/lib/changebit.S b/libdde-linux26/contrib/arch/arm/lib/changebit.S new file mode 100644 index 00000000..80f3115c --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/lib/changebit.S @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/lib/changebit.S + * + * Copyright (C) 1995-1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include "bitops.h" + .text + +/* Purpose : Function to change a bit + * Prototype: int change_bit(int bit, void *addr) + */ +ENTRY(_change_bit_be) + eor r0, r0, #0x18 @ big endian byte ordering +ENTRY(_change_bit_le) + bitop eor +ENDPROC(_change_bit_be) +ENDPROC(_change_bit_le) diff --git a/libdde-linux26/contrib/arch/arm/lib/clearbit.S b/libdde-linux26/contrib/arch/arm/lib/clearbit.S new file mode 100644 index 00000000..1a63e43a --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/lib/clearbit.S @@ -0,0 +1,24 @@ +/* + * linux/arch/arm/lib/clearbit.S + * + * Copyright (C) 1995-1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include "bitops.h" + .text + +/* + * Purpose : Function to clear a bit + * Prototype: int clear_bit(int bit, void *addr) + */ +ENTRY(_clear_bit_be) + eor r0, r0, #0x18 @ big endian byte ordering +ENTRY(_clear_bit_le) + bitop bic +ENDPROC(_clear_bit_be) +ENDPROC(_clear_bit_le) diff --git a/libdde-linux26/contrib/arch/arm/lib/div64.S b/libdde-linux26/contrib/arch/arm/lib/div64.S new file mode 100644 index 00000000..1425e789 --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/lib/div64.S @@ -0,0 +1,201 @@ +/* + * linux/arch/arm/lib/div64.S + * + * Optimized computation of 64-bit dividend / 32-bit divisor + * + * Author: Nicolas Pitre + * Created: Oct 5, 2003 + * Copyright: Monta Vista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#ifdef __ARMEB__ +#define xh r0 +#define xl r1 +#define yh r2 +#define yl r3 +#else +#define xl r0 +#define xh r1 +#define yl r2 +#define yh r3 +#endif + +/* + * __do_div64: perform a division with 64-bit dividend and 32-bit divisor. + * + * Note: Calling convention is totally non standard for optimal code. + * This is meant to be used by do_div() from include/asm/div64.h only. + * + * Input parameters: + * xh-xl = dividend (clobbered) + * r4 = divisor (preserved) + * + * Output values: + * yh-yl = result + * xh = remainder + * + * Clobbered regs: xl, ip + */ + +ENTRY(__do_div64) + + @ Test for easy paths first. + subs ip, r4, #1 + bls 9f @ divisor is 0 or 1 + tst ip, r4 + beq 8f @ divisor is power of 2 + + @ See if we need to handle upper 32-bit result. + cmp xh, r4 + mov yh, #0 + blo 3f + + @ Align divisor with upper part of dividend. + @ The aligned divisor is stored in yl preserving the original. + @ The bit position is stored in ip. + +#if __LINUX_ARM_ARCH__ >= 5 + + clz yl, r4 + clz ip, xh + sub yl, yl, ip + mov ip, #1 + mov ip, ip, lsl yl + mov yl, r4, lsl yl + +#else + + mov yl, r4 + mov ip, #1 +1: cmp yl, #0x80000000 + cmpcc yl, xh + movcc yl, yl, lsl #1 + movcc ip, ip, lsl #1 + bcc 1b + +#endif + + @ The division loop for needed upper bit positions. + @ Break out early if dividend reaches 0. +2: cmp xh, yl + orrcs yh, yh, ip + subcss xh, xh, yl + movnes ip, ip, lsr #1 + mov yl, yl, lsr #1 + bne 2b + + @ See if we need to handle lower 32-bit result. +3: cmp xh, #0 + mov yl, #0 + cmpeq xl, r4 + movlo xh, xl + movlo pc, lr + + @ The division loop for lower bit positions. + @ Here we shift remainer bits leftwards rather than moving the + @ divisor for comparisons, considering the carry-out bit as well. + mov ip, #0x80000000 +4: movs xl, xl, lsl #1 + adcs xh, xh, xh + beq 6f + cmpcc xh, r4 +5: orrcs yl, yl, ip + subcs xh, xh, r4 + movs ip, ip, lsr #1 + bne 4b + mov pc, lr + + @ The top part of remainder became zero. If carry is set + @ (the 33th bit) this is a false positive so resume the loop. + @ Otherwise, if lower part is also null then we are done. +6: bcs 5b + cmp xl, #0 + moveq pc, lr + + @ We still have remainer bits in the low part. Bring them up. + +#if __LINUX_ARM_ARCH__ >= 5 + + clz xh, xl @ we know xh is zero here so... + add xh, xh, #1 + mov xl, xl, lsl xh + mov ip, ip, lsr xh + +#else + +7: movs xl, xl, lsl #1 + mov ip, ip, lsr #1 + bcc 7b + +#endif + + @ Current remainder is now 1. It is worthless to compare with + @ divisor at this point since divisor can not be smaller than 3 here. + @ If possible, branch for another shift in the division loop. + @ If no bit position left then we are done. + movs ip, ip, lsr #1 + mov xh, #1 + bne 4b + mov pc, lr + +8: @ Division by a power of 2: determine what that divisor order is + @ then simply shift values around + +#if __LINUX_ARM_ARCH__ >= 5 + + clz ip, r4 + rsb ip, ip, #31 + +#else + + mov yl, r4 + cmp r4, #(1 << 16) + mov ip, #0 + movhs yl, yl, lsr #16 + movhs ip, #16 + + cmp yl, #(1 << 8) + movhs yl, yl, lsr #8 + addhs ip, ip, #8 + + cmp yl, #(1 << 4) + movhs yl, yl, lsr #4 + addhs ip, ip, #4 + + cmp yl, #(1 << 2) + addhi ip, ip, #3 + addls ip, ip, yl, lsr #1 + +#endif + + mov yh, xh, lsr ip + mov yl, xl, lsr ip + rsb ip, ip, #32 + orr yl, yl, xh, lsl ip + mov xh, xl, lsl ip + mov xh, xh, lsr ip + mov pc, lr + + @ eq -> division by 1: obvious enough... +9: moveq yl, xl + moveq yh, xh + moveq xh, #0 + moveq pc, lr + + @ Division by 0: + str lr, [sp, #-8]! + bl __div0 + + @ as wrong as it could be... + mov yl, #0 + mov yh, #0 + mov xh, #0 + ldr pc, [sp], #8 + +ENDPROC(__do_div64) diff --git a/libdde-linux26/contrib/arch/arm/lib/findbit.S b/libdde-linux26/contrib/arch/arm/lib/findbit.S new file mode 100644 index 00000000..8c4defc4 --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/lib/findbit.S @@ -0,0 +1,176 @@ +/* + * linux/arch/arm/lib/findbit.S + * + * Copyright (C) 1995-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * 16th March 2001 - John Ripley + * Fixed so that "size" is an exclusive not an inclusive quantity. + * All users of these functions expect exclusive sizes, and may + * also call with zero size. + * Reworked by rmk. + */ +#include +#include + .text + +/* + * Purpose : Find a 'zero' bit + * Prototype: int find_first_zero_bit(void *addr, unsigned int maxbit); + */ +ENTRY(_find_first_zero_bit_le) + teq r1, #0 + beq 3f + mov r2, #0 +1: ldrb r3, [r0, r2, lsr #3] + eors r3, r3, #0xff @ invert bits + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: cmp r2, r1 @ any more? + blo 1b +3: mov r0, r1 @ no free bits + mov pc, lr +ENDPROC(_find_first_zero_bit_le) + +/* + * Purpose : Find next 'zero' bit + * Prototype: int find_next_zero_bit(void *addr, unsigned int maxbit, int offset) + */ +ENTRY(_find_next_zero_bit_le) + teq r1, #0 + beq 3b + ands ip, r2, #7 + beq 1b @ If new byte, goto old routine + ldrb r3, [r0, r2, lsr #3] + eor r3, r3, #0xff @ now looking for a 1 bit + movs r3, r3, lsr ip @ shift off unused bits + bne .L_found + orr r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit +ENDPROC(_find_next_zero_bit_le) + +/* + * Purpose : Find a 'one' bit + * Prototype: int find_first_bit(const unsigned long *addr, unsigned int maxbit); + */ +ENTRY(_find_first_bit_le) + teq r1, #0 + beq 3f + mov r2, #0 +1: ldrb r3, [r0, r2, lsr #3] + movs r3, r3 + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: cmp r2, r1 @ any more? + blo 1b +3: mov r0, r1 @ no free bits + mov pc, lr +ENDPROC(_find_first_bit_le) + +/* + * Purpose : Find next 'one' bit + * Prototype: int find_next_zero_bit(void *addr, unsigned int maxbit, int offset) + */ +ENTRY(_find_next_bit_le) + teq r1, #0 + beq 3b + ands ip, r2, #7 + beq 1b @ If new byte, goto old routine + ldrb r3, [r0, r2, lsr #3] + movs r3, r3, lsr ip @ shift off unused bits + bne .L_found + orr r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit +ENDPROC(_find_next_bit_le) + +#ifdef __ARMEB__ + +ENTRY(_find_first_zero_bit_be) + teq r1, #0 + beq 3f + mov r2, #0 +1: eor r3, r2, #0x18 @ big endian byte ordering + ldrb r3, [r0, r3, lsr #3] + eors r3, r3, #0xff @ invert bits + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: cmp r2, r1 @ any more? + blo 1b +3: mov r0, r1 @ no free bits + mov pc, lr +ENDPROC(_find_first_zero_bit_be) + +ENTRY(_find_next_zero_bit_be) + teq r1, #0 + beq 3b + ands ip, r2, #7 + beq 1b @ If new byte, goto old routine + eor r3, r2, #0x18 @ big endian byte ordering + ldrb r3, [r0, r3, lsr #3] + eor r3, r3, #0xff @ now looking for a 1 bit + movs r3, r3, lsr ip @ shift off unused bits + bne .L_found + orr r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit +ENDPROC(_find_next_zero_bit_be) + +ENTRY(_find_first_bit_be) + teq r1, #0 + beq 3f + mov r2, #0 +1: eor r3, r2, #0x18 @ big endian byte ordering + ldrb r3, [r0, r3, lsr #3] + movs r3, r3 + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: cmp r2, r1 @ any more? + blo 1b +3: mov r0, r1 @ no free bits + mov pc, lr +ENDPROC(_find_first_bit_be) + +ENTRY(_find_next_bit_be) + teq r1, #0 + beq 3b + ands ip, r2, #7 + beq 1b @ If new byte, goto old routine + eor r3, r2, #0x18 @ big endian byte ordering + ldrb r3, [r0, r3, lsr #3] + movs r3, r3, lsr ip @ shift off unused bits + bne .L_found + orr r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit +ENDPROC(_find_next_bit_be) + +#endif + +/* + * One or more bits in the LSB of r3 are assumed to be set. + */ +.L_found: +#if __LINUX_ARM_ARCH__ >= 5 + rsb r1, r3, #0 + and r3, r3, r1 + clz r3, r3 + rsb r3, r3, #31 + add r0, r2, r3 +#else + tst r3, #0x0f + addeq r2, r2, #4 + movne r3, r3, lsl #4 + tst r3, #0x30 + addeq r2, r2, #2 + movne r3, r3, lsl #2 + tst r3, #0x40 + addeq r2, r2, #1 + mov r0, r2 +#endif + mov pc, lr + diff --git a/libdde-linux26/contrib/arch/arm/lib/memzero.S b/libdde-linux26/contrib/arch/arm/lib/memzero.S new file mode 100644 index 00000000..3fbdef5f --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/lib/memzero.S @@ -0,0 +1,125 @@ +/* + * linux/arch/arm/lib/memzero.S + * + * Copyright (C) 1995-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include + + .text + .align 5 + .word 0 +/* + * Align the pointer in r0. r3 contains the number of bytes that we are + * mis-aligned by, and r1 is the number of bytes. If r1 < 4, then we + * don't bother; we use byte stores instead. + */ +1: subs r1, r1, #4 @ 1 do we have enough + blt 5f @ 1 bytes to align with? + cmp r3, #2 @ 1 + strltb r2, [r0], #1 @ 1 + strleb r2, [r0], #1 @ 1 + strb r2, [r0], #1 @ 1 + add r1, r1, r3 @ 1 (r1 = r1 - (4 - r3)) +/* + * The pointer is now aligned and the length is adjusted. Try doing the + * memzero again. + */ + +ENTRY(__memzero) + mov r2, #0 @ 1 + ands r3, r0, #3 @ 1 unaligned? + bne 1b @ 1 +/* + * r3 = 0, and we know that the pointer in r0 is aligned to a word boundary. + */ + cmp r1, #16 @ 1 we can skip this chunk if we + blt 4f @ 1 have < 16 bytes + +#if ! CALGN(1)+0 + +/* + * We need an extra register for this loop - save the return address and + * use the LR + */ + str lr, [sp, #-4]! @ 1 + mov ip, r2 @ 1 + mov lr, r2 @ 1 + +3: subs r1, r1, #64 @ 1 write 32 bytes out per loop + stmgeia r0!, {r2, r3, ip, lr} @ 4 + stmgeia r0!, {r2, r3, ip, lr} @ 4 + stmgeia r0!, {r2, r3, ip, lr} @ 4 + stmgeia r0!, {r2, r3, ip, lr} @ 4 + bgt 3b @ 1 + ldmeqfd sp!, {pc} @ 1/2 quick exit +/* + * No need to correct the count; we're only testing bits from now on + */ + tst r1, #32 @ 1 + stmneia r0!, {r2, r3, ip, lr} @ 4 + stmneia r0!, {r2, r3, ip, lr} @ 4 + tst r1, #16 @ 1 16 bytes or more? + stmneia r0!, {r2, r3, ip, lr} @ 4 + ldr lr, [sp], #4 @ 1 + +#else + +/* + * This version aligns the destination pointer in order to write + * whole cache lines at once. + */ + + stmfd sp!, {r4-r7, lr} + mov r4, r2 + mov r5, r2 + mov r6, r2 + mov r7, r2 + mov ip, r2 + mov lr, r2 + + cmp r1, #96 + andgts ip, r0, #31 + ble 3f + + rsb ip, ip, #32 + sub r1, r1, ip + movs ip, ip, lsl #(32 - 4) + stmcsia r0!, {r4, r5, r6, r7} + stmmiia r0!, {r4, r5} + movs ip, ip, lsl #2 + strcs r2, [r0], #4 + +3: subs r1, r1, #64 + stmgeia r0!, {r2-r7, ip, lr} + stmgeia r0!, {r2-r7, ip, lr} + bgt 3b + ldmeqfd sp!, {r4-r7, pc} + + tst r1, #32 + stmneia r0!, {r2-r7, ip, lr} + tst r1, #16 + stmneia r0!, {r4-r7} + ldmfd sp!, {r4-r7, lr} + +#endif + +4: tst r1, #8 @ 1 8 bytes or more? + stmneia r0!, {r2, r3} @ 2 + tst r1, #4 @ 1 4 bytes or more? + strne r2, [r0], #4 @ 1 +/* + * When we get here, we've got less than 4 bytes to zero. We + * may have an unaligned pointer as well. + */ +5: tst r1, #2 @ 1 2 bytes or more? + strneb r2, [r0], #1 @ 1 + strneb r2, [r0], #1 @ 1 + tst r1, #1 @ 1 a byte left over + strneb r2, [r0], #1 @ 1 + mov pc, lr @ 1 +ENDPROC(__memzero) diff --git a/libdde-linux26/contrib/arch/arm/lib/setbit.S b/libdde-linux26/contrib/arch/arm/lib/setbit.S new file mode 100644 index 00000000..1dd7176c --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/lib/setbit.S @@ -0,0 +1,24 @@ +/* + * linux/arch/arm/lib/setbit.S + * + * Copyright (C) 1995-1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include "bitops.h" + .text + +/* + * Purpose : Function to set a bit + * Prototype: int set_bit(int bit, void *addr) + */ +ENTRY(_set_bit_be) + eor r0, r0, #0x18 @ big endian byte ordering +ENTRY(_set_bit_le) + bitop orr +ENDPROC(_set_bit_be) +ENDPROC(_set_bit_le) diff --git a/libdde-linux26/contrib/arch/arm/lib/testchangebit.S b/libdde-linux26/contrib/arch/arm/lib/testchangebit.S new file mode 100644 index 00000000..5c98dc56 --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/lib/testchangebit.S @@ -0,0 +1,20 @@ +/* + * linux/arch/arm/lib/testchangebit.S + * + * Copyright (C) 1995-1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include "bitops.h" + .text + +ENTRY(_test_and_change_bit_be) + eor r0, r0, #0x18 @ big endian byte ordering +ENTRY(_test_and_change_bit_le) + testop eor, strb +ENDPROC(_test_and_change_bit_be) +ENDPROC(_test_and_change_bit_le) diff --git a/libdde-linux26/contrib/arch/arm/lib/testclearbit.S b/libdde-linux26/contrib/arch/arm/lib/testclearbit.S new file mode 100644 index 00000000..543d7094 --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/lib/testclearbit.S @@ -0,0 +1,20 @@ +/* + * linux/arch/arm/lib/testclearbit.S + * + * Copyright (C) 1995-1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include "bitops.h" + .text + +ENTRY(_test_and_clear_bit_be) + eor r0, r0, #0x18 @ big endian byte ordering +ENTRY(_test_and_clear_bit_le) + testop bicne, strneb +ENDPROC(_test_and_clear_bit_be) +ENDPROC(_test_and_clear_bit_le) diff --git a/libdde-linux26/contrib/arch/arm/lib/testsetbit.S b/libdde-linux26/contrib/arch/arm/lib/testsetbit.S new file mode 100644 index 00000000..0b3f3904 --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/lib/testsetbit.S @@ -0,0 +1,20 @@ +/* + * linux/arch/arm/lib/testsetbit.S + * + * Copyright (C) 1995-1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include "bitops.h" + .text + +ENTRY(_test_and_set_bit_be) + eor r0, r0, #0x18 @ big endian byte ordering +ENTRY(_test_and_set_bit_le) + testop orreq, streqb +ENDPROC(_test_and_set_bit_be) +ENDPROC(_test_and_set_bit_le) diff --git a/libdde-linux26/contrib/arch/arm/mach-realview/clock.c b/libdde-linux26/contrib/arch/arm/mach-realview/clock.c new file mode 100644 index 00000000..a7043115 --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/mach-realview/clock.c @@ -0,0 +1,64 @@ +/* + * linux/arch/arm/mach-realview/clock.c + * + * Copyright (C) 2004 ARM Limited. + * Written by Deep Blue Solutions Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clock.h" + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + struct icst307_vco vco; + vco = icst307_khz_to_vco(clk->params, rate / 1000); + return icst307_khz(clk->params, vco) * 1000; +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EIO; + + if (clk->setvco) { + struct icst307_vco vco; + + vco = icst307_khz_to_vco(clk->params, rate / 1000); + clk->rate = icst307_khz(clk->params, vco) * 1000; + clk->setvco(clk, vco); + ret = 0; + } + return ret; +} +EXPORT_SYMBOL(clk_set_rate); diff --git a/libdde-linux26/contrib/arch/arm/mach-realview/clock.h b/libdde-linux26/contrib/arch/arm/mach-realview/clock.h new file mode 100644 index 00000000..ebbb0f06 --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/mach-realview/clock.h @@ -0,0 +1,19 @@ +/* + * linux/arch/arm/mach-realview/clock.h + * + * Copyright (C) 2004 ARM Limited. + * Written by Deep Blue Solutions Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +struct module; +struct icst307_params; + +struct clk { + unsigned long rate; + const struct icst307_params *params; + void *data; + void (*setvco)(struct clk *, struct icst307_vco vco); +}; diff --git a/libdde-linux26/contrib/arch/arm/mach-realview/core.h b/libdde-linux26/contrib/arch/arm/mach-realview/core.h new file mode 100644 index 00000000..44269b16 --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/mach-realview/core.h @@ -0,0 +1,66 @@ +/* + * linux/arch/arm/mach-realview/core.h + * + * Copyright (C) 2004 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_REALVIEW_H +#define __ASM_ARCH_REALVIEW_H + +#include +#include + +#include + +#define AMBA_DEVICE(name,busid,base,plat) \ +static struct amba_device name##_device = { \ + .dev = { \ + .coherent_dma_mask = ~0, \ + .init_name = busid, \ + .platform_data = plat, \ + }, \ + .res = { \ + .start = REALVIEW_##base##_BASE, \ + .end = (REALVIEW_##base##_BASE) + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, \ + .dma_mask = ~0, \ + .irq = base##_IRQ, \ + /* .dma = base##_DMA,*/ \ +} + +extern struct platform_device realview_flash_device; +extern struct platform_device realview_i2c_device; +extern struct mmc_platform_data realview_mmc0_plat_data; +extern struct mmc_platform_data realview_mmc1_plat_data; +extern struct clcd_board clcd_plat_data; +extern void __iomem *gic_cpu_base_addr; +#ifdef CONFIG_LOCAL_TIMERS +extern void __iomem *twd_base; +#endif +extern void __iomem *timer0_va_base; +extern void __iomem *timer1_va_base; +extern void __iomem *timer2_va_base; +extern void __iomem *timer3_va_base; + +extern void realview_leds_event(led_event_t ledevt); +extern void realview_timer_init(unsigned int timer_irq); +extern int realview_flash_register(struct resource *res, u32 num); +extern int realview_eth_register(const char *name, struct resource *res); + +#endif diff --git a/libdde-linux26/contrib/arch/arm/mach-realview/realview_eb.c b/libdde-linux26/contrib/arch/arm/mach-realview/realview_eb.c new file mode 100644 index 00000000..bed39ed9 --- /dev/null +++ b/libdde-linux26/contrib/arch/arm/mach-realview/realview_eb.c @@ -0,0 +1,389 @@ +/* + * linux/arch/arm/mach-realview/realview_eb.c + * + * Copyright (C) 2004 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "core.h" +#include "clock.h" + +static struct map_desc realview_eb_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), + .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), + .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#ifdef CONFIG_DEBUG_LL + { + .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + } +#endif +}; + +static struct map_desc realview_eb11mp_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE), + .length = SZ_8K, + .type = MT_DEVICE, + } +}; + +static void __init realview_eb_map_io(void) +{ + iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc)); + if (core_tile_eb11mp() || core_tile_a9mp()) + iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc)); +} + +/* + * RealView EB AMBA devices + */ + +/* + * These devices are connected via the core APB bridge + */ +#define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ } +#define GPIO2_DMA { 0, 0 } +#define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ } +#define GPIO3_DMA { 0, 0 } + +#define AACI_IRQ { IRQ_EB_AACI, NO_IRQ } +#define AACI_DMA { 0x80, 0x81 } +#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B } +#define MMCI0_DMA { 0x84, 0 } +#define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ } +#define KMI0_DMA { 0, 0 } +#define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ } +#define KMI1_DMA { 0, 0 } + +/* + * These devices are connected directly to the multi-layer AHB switch + */ +#define EB_SMC_IRQ { NO_IRQ, NO_IRQ } +#define EB_SMC_DMA { 0, 0 } +#define MPMC_IRQ { NO_IRQ, NO_IRQ } +#define MPMC_DMA { 0, 0 } +#define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } +#define EB_CLCD_DMA { 0, 0 } +#define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } +#define DMAC_DMA { 0, 0 } + +/* + * These devices are connected via the core APB bridge + */ +#define SCTL_IRQ { NO_IRQ, NO_IRQ } +#define SCTL_DMA { 0, 0 } +#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } +#define EB_WATCHDOG_DMA { 0, 0 } +#define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } +#define EB_GPIO0_DMA { 0, 0 } +#define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } +#define GPIO1_DMA { 0, 0 } +#define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ } +#define EB_RTC_DMA { 0, 0 } + +/* + * These devices are connected via the DMA APB bridge + */ +#define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } +#define SCI_DMA { 7, 6 } +#define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ } +#define EB_UART0_DMA { 15, 14 } +#define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ } +#define EB_UART1_DMA { 13, 12 } +#define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ } +#define EB_UART2_DMA { 11, 10 } +#define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ } +#define EB_UART3_DMA { 0x86, 0x87 } +#define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ } +#define EB_SSP_DMA { 9, 8 } + +/* FPGA Primecells */ +AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); +AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); +AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); +AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); +AMBA_DEVICE(uart3, "fpga:09", EB_UART3, NULL); + +/* DevChip Primecells */ +AMBA_DEVICE(smc, "dev:00", EB_SMC, NULL); +AMBA_DEVICE(clcd, "dev:20", EB_CLCD, &clcd_plat_data); +AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); +AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); +AMBA_DEVICE(wdog, "dev:e1", EB_WATCHDOG, NULL); +AMBA_DEVICE(gpio0, "dev:e4", EB_GPIO0, NULL); +AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); +AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); +AMBA_DEVICE(rtc, "dev:e8", EB_RTC, NULL); +AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); +AMBA_DEVICE(uart0, "dev:f1", EB_UART0, NULL); +AMBA_DEVICE(uart1, "dev:f2", EB_UART1, NULL); +AMBA_DEVICE(uart2, "dev:f3", EB_UART2, NULL); +AMBA_DEVICE(ssp0, "dev:f4", EB_SSP, NULL); + +static struct amba_device *amba_devs[] __initdata = { + &dmac_device, + &uart0_device, + &uart1_device, + &uart2_device, + &uart3_device, + &smc_device, + &clcd_device, + &sctl_device, + &wdog_device, + &gpio0_device, + &gpio1_device, + &gpio2_device, + &rtc_device, + &sci0_device, + &ssp0_device, + &aaci_device, + &mmc0_device, + &kmi0_device, + &kmi1_device, +}; + +/* + * RealView EB platform devices + */ +static struct resource realview_eb_flash_resource = { + .start = REALVIEW_EB_FLASH_BASE, + .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct resource realview_eb_eth_resources[] = { + [0] = { + .start = REALVIEW_EB_ETH_BASE, + .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_EB_ETH, + .end = IRQ_EB_ETH, + .flags = IORESOURCE_IRQ, + }, +}; + +/* + * Detect and register the correct Ethernet device. RealView/EB rev D + * platforms use the newer SMSC LAN9118 Ethernet chip + */ +static int eth_device_register(void) +{ + void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K); + const char *name = NULL; + u32 idrev; + + if (!eth_addr) + return -ENOMEM; + + idrev = readl(eth_addr + 0x50); + if ((idrev & 0xFFFF0000) != 0x01180000) + /* SMSC LAN9118 not present, use LAN91C111 instead */ + name = "smc91x"; + + iounmap(eth_addr); + return realview_eth_register(name, realview_eb_eth_resources); +} + +static void __init gic_init_irq(void) +{ + if (core_tile_eb11mp() || core_tile_a9mp()) { + unsigned int pldctrl; + + /* new irq mode */ + writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); + pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1); + pldctrl |= 0x00800000; + writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1); + writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); + + /* core tile GIC, primary */ + gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE); + gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29); + gic_cpu_init(0, gic_cpu_base_addr); + +#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB + /* board GIC, secondary */ + gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64); + gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE)); + gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); +#endif + } else { + /* board GIC, primary */ + gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE); + gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29); + gic_cpu_init(0, gic_cpu_base_addr); + } +} + +/* + * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile + */ +static void realview_eb11mp_fixup(void) +{ + /* AMBA devices */ + dmac_device.irq[0] = IRQ_EB11MP_DMA; + uart0_device.irq[0] = IRQ_EB11MP_UART0; + uart1_device.irq[0] = IRQ_EB11MP_UART1; + uart2_device.irq[0] = IRQ_EB11MP_UART2; + uart3_device.irq[0] = IRQ_EB11MP_UART3; + clcd_device.irq[0] = IRQ_EB11MP_CLCD; + wdog_device.irq[0] = IRQ_EB11MP_WDOG; + gpio0_device.irq[0] = IRQ_EB11MP_GPIO0; + gpio1_device.irq[0] = IRQ_EB11MP_GPIO1; + gpio2_device.irq[0] = IRQ_EB11MP_GPIO2; + rtc_device.irq[0] = IRQ_EB11MP_RTC; + sci0_device.irq[0] = IRQ_EB11MP_SCI; + ssp0_device.irq[0] = IRQ_EB11MP_SSP; + aaci_device.irq[0] = IRQ_EB11MP_AACI; + mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A; + mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B; + kmi0_device.irq[0] = IRQ_EB11MP_KMI0; + kmi1_device.irq[0] = IRQ_EB11MP_KMI1; + + /* platform devices */ + realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH; + realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH; +} + +static void __init realview_eb_timer_init(void) +{ + unsigned int timer_irq; + + timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE); + timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20; + timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE); + timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20; + + if (core_tile_eb11mp() || core_tile_a9mp()) { +#ifdef CONFIG_LOCAL_TIMERS + twd_base = __io_address(REALVIEW_EB11MP_TWD_BASE); +#endif + timer_irq = IRQ_EB11MP_TIMER0_1; + } else + timer_irq = IRQ_EB_TIMER0_1; + + realview_timer_init(timer_irq); +} + +static struct sys_timer realview_eb_timer = { + .init = realview_eb_timer_init, +}; + +static void __init realview_eb_init(void) +{ + int i; + + if (core_tile_eb11mp() || core_tile_a9mp()) { + realview_eb11mp_fixup(); + +#ifdef CONFIG_CACHE_L2X0 + /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled + * Bits: .... ...0 0111 1001 0000 .... .... .... */ + l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); +#endif + } + + realview_flash_register(&realview_eb_flash_resource, 1); + platform_device_register(&realview_i2c_device); + eth_device_register(); + + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; + amba_device_register(d, &iomem_resource); + } + +#ifdef CONFIG_LEDS + leds_event = realview_leds_event; +#endif +} + +MACHINE_START(REALVIEW_EB, "ARM-RealView EB") + /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ + .phys_io = REALVIEW_EB_UART0_BASE, + .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x00000100, + .map_io = realview_eb_map_io, + .init_irq = gic_init_irq, + .timer = &realview_eb_timer, + .init_machine = realview_eb_init, +MACHINE_END diff --git a/libdde-linux26/contrib/arch/x86/include/Makefile b/libdde-linux26/contrib/arch/x86/include/Makefile new file mode 100644 index 00000000..92d41a6d --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/Makefile @@ -0,0 +1,13 @@ +PKGDIR ?= ../../../.. +L4DIR ?= $(PKGDIR) + +# Force these include files to appear in a special subfolder of dde/ +INSTALL_INC_PREFIX = linux-headers/ + +include $(L4DIR)/mk/include.mk + +#MAKELINK = if [ ! $1 -ef $2 ] ; then ln -$(if $(VERBOSE),v)sf $2 $1 ; fi +#ARCH = $(BUILD_ARCH) +# +#all:: +# $(VERBOSE)$(MKDIR) $(INSTALLDIR_LOCAL)/$(ARCH)/$(INSTALL_INC_PREFIX) diff --git a/libdde-linux26/contrib/arch/x86/include/asm/Kbuild b/libdde-linux26/contrib/arch/x86/include/asm/Kbuild new file mode 100644 index 00000000..4a8e80cd --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/Kbuild @@ -0,0 +1,24 @@ +include include/asm-generic/Kbuild.asm + +header-y += boot.h +header-y += bootparam.h +header-y += debugreg.h +header-y += ldt.h +header-y += msr-index.h +header-y += prctl.h +header-y += ptrace-abi.h +header-y += sigcontext32.h +header-y += ucontext.h +header-y += processor-flags.h + +unifdef-y += e820.h +unifdef-y += ist.h +unifdef-y += mce.h +unifdef-y += msr.h +unifdef-y += mtrr.h +unifdef-y += posix_types_32.h +unifdef-y += posix_types_64.h +unifdef-y += unistd_32.h +unifdef-y += unistd_64.h +unifdef-y += vm86.h +unifdef-y += vsyscall.h diff --git a/libdde-linux26/contrib/arch/x86/include/asm/a.out-core.h b/libdde-linux26/contrib/arch/x86/include/asm/a.out-core.h new file mode 100644 index 00000000..3c601f82 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/a.out-core.h @@ -0,0 +1,71 @@ +/* a.out coredump register dumper + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_X86_A_OUT_CORE_H +#define _ASM_X86_A_OUT_CORE_H + +#ifdef __KERNEL__ +#ifdef CONFIG_X86_32 + +#include +#include + +/* + * fill in the user structure for an a.out core dump + */ +static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) +{ +/* changed the size calculations - should hopefully work better. lbt */ + dump->magic = CMAGIC; + dump->start_code = 0; + dump->start_stack = regs->sp & ~(PAGE_SIZE - 1); + dump->u_tsize = ((unsigned long)current->mm->end_code) >> PAGE_SHIFT; + dump->u_dsize = ((unsigned long)(current->mm->brk + (PAGE_SIZE - 1))) + >> PAGE_SHIFT; + dump->u_dsize -= dump->u_tsize; + dump->u_ssize = 0; + dump->u_debugreg[0] = current->thread.debugreg0; + dump->u_debugreg[1] = current->thread.debugreg1; + dump->u_debugreg[2] = current->thread.debugreg2; + dump->u_debugreg[3] = current->thread.debugreg3; + dump->u_debugreg[4] = 0; + dump->u_debugreg[5] = 0; + dump->u_debugreg[6] = current->thread.debugreg6; + dump->u_debugreg[7] = current->thread.debugreg7; + + if (dump->start_stack < TASK_SIZE) + dump->u_ssize = ((unsigned long)(TASK_SIZE - dump->start_stack)) + >> PAGE_SHIFT; + + dump->regs.bx = regs->bx; + dump->regs.cx = regs->cx; + dump->regs.dx = regs->dx; + dump->regs.si = regs->si; + dump->regs.di = regs->di; + dump->regs.bp = regs->bp; + dump->regs.ax = regs->ax; + dump->regs.ds = (u16)regs->ds; + dump->regs.es = (u16)regs->es; + dump->regs.fs = (u16)regs->fs; + savesegment(gs, dump->regs.gs); + dump->regs.orig_ax = regs->orig_ax; + dump->regs.ip = regs->ip; + dump->regs.cs = (u16)regs->cs; + dump->regs.flags = regs->flags; + dump->regs.sp = regs->sp; + dump->regs.ss = (u16)regs->ss; + + dump->u_fpvalid = dump_fpu(regs, &dump->i387); +} + +#endif /* CONFIG_X86_32 */ +#endif /* __KERNEL__ */ +#endif /* _ASM_X86_A_OUT_CORE_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/a.out.h b/libdde-linux26/contrib/arch/x86/include/asm/a.out.h new file mode 100644 index 00000000..4684f97a --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/a.out.h @@ -0,0 +1,20 @@ +#ifndef _ASM_X86_A_OUT_H +#define _ASM_X86_A_OUT_H + +struct exec +{ + unsigned int a_info; /* Use macros N_MAGIC, etc for access */ + unsigned a_text; /* length of text, in bytes */ + unsigned a_data; /* length of data, in bytes */ + unsigned a_bss; /* length of uninitialized data area for file, in bytes */ + unsigned a_syms; /* length of symbol table data in file, in bytes */ + unsigned a_entry; /* start address */ + unsigned a_trsize; /* length of relocation info for text, in bytes */ + unsigned a_drsize; /* length of relocation info for data, in bytes */ +}; + +#define N_TRSIZE(a) ((a).a_trsize) +#define N_DRSIZE(a) ((a).a_drsize) +#define N_SYMSIZE(a) ((a).a_syms) + +#endif /* _ASM_X86_A_OUT_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/acpi.h b/libdde-linux26/contrib/arch/x86/include/asm/acpi.h new file mode 100644 index 00000000..98306814 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/acpi.h @@ -0,0 +1,177 @@ +#ifndef _ASM_X86_ACPI_H +#define _ASM_X86_ACPI_H + +/* + * Copyright (C) 2001 Paul Diefenbaugh + * Copyright (C) 2001 Patrick Mochel + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + */ +#include + +#include +#include +#include +#include + +#define COMPILER_DEPENDENT_INT64 long long +#define COMPILER_DEPENDENT_UINT64 unsigned long long + +/* + * Calling conventions: + * + * ACPI_SYSTEM_XFACE - Interfaces to host OS (handlers, threads) + * ACPI_EXTERNAL_XFACE - External ACPI interfaces + * ACPI_INTERNAL_XFACE - Internal ACPI interfaces + * ACPI_INTERNAL_VAR_XFACE - Internal variable-parameter list interfaces + */ +#define ACPI_SYSTEM_XFACE +#define ACPI_EXTERNAL_XFACE +#define ACPI_INTERNAL_XFACE +#define ACPI_INTERNAL_VAR_XFACE + +/* Asm macros */ + +#define ACPI_ASM_MACROS +#define BREAKPOINT3 +#define ACPI_DISABLE_IRQS() local_irq_disable() +#define ACPI_ENABLE_IRQS() local_irq_enable() +#define ACPI_FLUSH_CPU_CACHE() wbinvd() + +int __acpi_acquire_global_lock(unsigned int *lock); +int __acpi_release_global_lock(unsigned int *lock); + +#define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \ + ((Acq) = __acpi_acquire_global_lock(&facs->global_lock)) + +#define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \ + ((Acq) = __acpi_release_global_lock(&facs->global_lock)) + +/* + * Math helper asm macros + */ +#define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \ + asm("divl %2;" \ + : "=a"(q32), "=d"(r32) \ + : "r"(d32), \ + "0"(n_lo), "1"(n_hi)) + + +#define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \ + asm("shrl $1,%2 ;" \ + "rcrl $1,%3;" \ + : "=r"(n_hi), "=r"(n_lo) \ + : "0"(n_hi), "1"(n_lo)) + +#ifdef CONFIG_ACPI +extern int acpi_lapic; +extern int acpi_ioapic; +extern int acpi_noirq; +extern int acpi_strict; +extern int acpi_disabled; +extern int acpi_ht; +extern int acpi_pci_disabled; +extern int acpi_skip_timer_override; +extern int acpi_use_timer_override; + +extern u8 acpi_sci_flags; +extern int acpi_sci_override_gsi; +void acpi_pic_sci_set_trigger(unsigned int, u16); + +static inline void disable_acpi(void) +{ + acpi_disabled = 1; + acpi_ht = 0; + acpi_pci_disabled = 1; + acpi_noirq = 1; +} + +/* Fixmap pages to reserve for ACPI boot-time tables (see fixmap.h) */ +#define FIX_ACPI_PAGES 4 + +extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq); + +static inline void acpi_noirq_set(void) { acpi_noirq = 1; } +static inline void acpi_disable_pci(void) +{ + acpi_pci_disabled = 1; + acpi_noirq_set(); +} + +/* routines for saving/restoring kernel state */ +extern int acpi_save_state_mem(void); +extern void acpi_restore_state_mem(void); + +extern unsigned long acpi_wakeup_address; + +/* early initialization routine */ +extern void acpi_reserve_bootmem(void); + +/* + * Check if the CPU can handle C2 and deeper + */ +static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) +{ + /* + * Early models (<=5) of AMD Opterons are not supposed to go into + * C2 state. + * + * Steppings 0x0A and later are good + */ + if (boot_cpu_data.x86 == 0x0F && + boot_cpu_data.x86_vendor == X86_VENDOR_AMD && + boot_cpu_data.x86_model <= 0x05 && + boot_cpu_data.x86_mask < 0x0A) + return 1; + else if (boot_cpu_has(X86_FEATURE_AMDC1E)) + return 1; + else + return max_cstate; +} + +#else /* !CONFIG_ACPI */ + +#define acpi_lapic 0 +#define acpi_ioapic 0 +static inline void acpi_noirq_set(void) { } +static inline void acpi_disable_pci(void) { } +static inline void disable_acpi(void) { } + +#endif /* !CONFIG_ACPI */ + +#define ARCH_HAS_POWER_INIT 1 + +struct bootnode; + +#ifdef CONFIG_ACPI_NUMA +extern int acpi_numa; +extern int acpi_scan_nodes(unsigned long start, unsigned long end); +#define NR_NODE_MEMBLKS (MAX_NUMNODES*2) +extern void acpi_fake_nodes(const struct bootnode *fake_nodes, + int num_nodes); +#else +static inline void acpi_fake_nodes(const struct bootnode *fake_nodes, + int num_nodes) +{ +} +#endif + +#define acpi_unlazy_tlb(x) leave_mm(x) + +#endif /* _ASM_X86_ACPI_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/agp.h b/libdde-linux26/contrib/arch/x86/include/asm/agp.h new file mode 100644 index 00000000..9825cd64 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/agp.h @@ -0,0 +1,35 @@ +#ifndef _ASM_X86_AGP_H +#define _ASM_X86_AGP_H + +#include +#include + +/* + * Functions to keep the agpgart mappings coherent with the MMU. The + * GART gives the CPU a physical alias of pages in memory. The alias + * region is mapped uncacheable. Make sure there are no conflicting + * mappings with different cachability attributes for the same + * page. This avoids data corruption on some CPUs. + */ + +#define map_page_into_agp(page) set_pages_uc(page, 1) +#define unmap_page_from_agp(page) set_pages_wb(page, 1) + +/* + * Could use CLFLUSH here if the cpu supports it. But then it would + * need to be called for each cacheline of the whole page so it may + * not be worth it. Would need a page for it. + */ +#define flush_agp_cache() wbinvd() + +/* Convert a physical address to an address suitable for the GART. */ +#define phys_to_gart(x) (x) +#define gart_to_phys(x) (x) + +/* GATT allocation. Returns/accepts GATT kernel virtual address. */ +#define alloc_gatt_pages(order) \ + ((char *)__get_free_pages(GFP_KERNEL, (order))) +#define free_gatt_pages(table, order) \ + free_pages((unsigned long)(table), (order)) + +#endif /* _ASM_X86_AGP_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/alternative-asm.h b/libdde-linux26/contrib/arch/x86/include/asm/alternative-asm.h new file mode 100644 index 00000000..e2077d34 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/alternative-asm.h @@ -0,0 +1,22 @@ +#ifdef __ASSEMBLY__ + +#ifdef CONFIG_X86_32 +# define X86_ALIGN .long +#else +# define X86_ALIGN .quad +#endif + +#ifdef CONFIG_SMP + .macro LOCK_PREFIX +1: lock + .section .smp_locks,"a" + .align 4 + X86_ALIGN 1b + .previous + .endm +#else + .macro LOCK_PREFIX + .endm +#endif + +#endif /* __ASSEMBLY__ */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/alternative.h b/libdde-linux26/contrib/arch/x86/include/asm/alternative.h new file mode 100644 index 00000000..f6aa18ea --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/alternative.h @@ -0,0 +1,183 @@ +#ifndef _ASM_X86_ALTERNATIVE_H +#define _ASM_X86_ALTERNATIVE_H + +#include +#include +#include + +/* + * Alternative inline assembly for SMP. + * + * The LOCK_PREFIX macro defined here replaces the LOCK and + * LOCK_PREFIX macros used everywhere in the source tree. + * + * SMP alternatives use the same data structures as the other + * alternatives and the X86_FEATURE_UP flag to indicate the case of a + * UP system running a SMP kernel. The existing apply_alternatives() + * works fine for patching a SMP kernel for UP. + * + * The SMP alternative tables can be kept after boot and contain both + * UP and SMP versions of the instructions to allow switching back to + * SMP at runtime, when hotplugging in a new CPU, which is especially + * useful in virtualized environments. + * + * The very common lock prefix is handled as special case in a + * separate table which is a pure address list without replacement ptr + * and size information. That keeps the table sizes small. + */ + +#ifdef CONFIG_SMP +#define LOCK_PREFIX \ + ".section .smp_locks,\"a\"\n" \ + _ASM_ALIGN "\n" \ + _ASM_PTR "661f\n" /* address */ \ + ".previous\n" \ + "661:\n\tlock; " + +#else /* ! CONFIG_SMP */ +#define LOCK_PREFIX "" +#endif + +/* This must be included *after* the definition of LOCK_PREFIX */ +#include + +struct alt_instr { + u8 *instr; /* original instruction */ + u8 *replacement; + u8 cpuid; /* cpuid bit set for replacement */ + u8 instrlen; /* length of original instruction */ + u8 replacementlen; /* length of new instruction, <= instrlen */ + u8 pad1; +#ifdef CONFIG_X86_64 + u32 pad2; +#endif +}; + +extern void alternative_instructions(void); +extern void apply_alternatives(struct alt_instr *start, struct alt_instr *end); + +struct module; + +#ifdef CONFIG_SMP +extern void alternatives_smp_module_add(struct module *mod, char *name, + void *locks, void *locks_end, + void *text, void *text_end); +extern void alternatives_smp_module_del(struct module *mod); +extern void alternatives_smp_switch(int smp); +#else +static inline void alternatives_smp_module_add(struct module *mod, char *name, + void *locks, void *locks_end, + void *text, void *text_end) {} +static inline void alternatives_smp_module_del(struct module *mod) {} +static inline void alternatives_smp_switch(int smp) {} +#endif /* CONFIG_SMP */ + +const unsigned char *const *find_nop_table(void); + +/* + * Alternative instructions for different CPU types or capabilities. + * + * This allows to use optimized instructions even on generic binary + * kernels. + * + * length of oldinstr must be longer or equal the length of newinstr + * It can be padded with nops as needed. + * + * For non barrier like inlines please define new variants + * without volatile and memory clobber. + */ +#define alternative(oldinstr, newinstr, feature) \ + asm volatile ("661:\n\t" oldinstr "\n662:\n" \ + ".section .altinstructions,\"a\"\n" \ + _ASM_ALIGN "\n" \ + _ASM_PTR "661b\n" /* label */ \ + _ASM_PTR "663f\n" /* new instruction */ \ + " .byte %c0\n" /* feature bit */ \ + " .byte 662b-661b\n" /* sourcelen */ \ + " .byte 664f-663f\n" /* replacementlen */ \ + ".previous\n" \ + ".section .altinstr_replacement,\"ax\"\n" \ + "663:\n\t" newinstr "\n664:\n" /* replacement */ \ + ".previous" :: "i" (feature) : "memory") + +/* + * Alternative inline assembly with input. + * + * Pecularities: + * No memory clobber here. + * Argument numbers start with 1. + * Best is to use constraints that are fixed size (like (%1) ... "r") + * If you use variable sized constraints like "m" or "g" in the + * replacement make sure to pad to the worst case length. + */ +#define alternative_input(oldinstr, newinstr, feature, input...) \ + asm volatile ("661:\n\t" oldinstr "\n662:\n" \ + ".section .altinstructions,\"a\"\n" \ + _ASM_ALIGN "\n" \ + _ASM_PTR "661b\n" /* label */ \ + _ASM_PTR "663f\n" /* new instruction */ \ + " .byte %c0\n" /* feature bit */ \ + " .byte 662b-661b\n" /* sourcelen */ \ + " .byte 664f-663f\n" /* replacementlen */ \ + ".previous\n" \ + ".section .altinstr_replacement,\"ax\"\n" \ + "663:\n\t" newinstr "\n664:\n" /* replacement */ \ + ".previous" :: "i" (feature), ##input) + +/* Like alternative_input, but with a single output argument */ +#define alternative_io(oldinstr, newinstr, feature, output, input...) \ + asm volatile ("661:\n\t" oldinstr "\n662:\n" \ + ".section .altinstructions,\"a\"\n" \ + _ASM_ALIGN "\n" \ + _ASM_PTR "661b\n" /* label */ \ + _ASM_PTR "663f\n" /* new instruction */ \ + " .byte %c[feat]\n" /* feature bit */ \ + " .byte 662b-661b\n" /* sourcelen */ \ + " .byte 664f-663f\n" /* replacementlen */ \ + ".previous\n" \ + ".section .altinstr_replacement,\"ax\"\n" \ + "663:\n\t" newinstr "\n664:\n" /* replacement */ \ + ".previous" : output : [feat] "i" (feature), ##input) + +/* + * use this macro(s) if you need more than one output parameter + * in alternative_io + */ +#define ASM_OUTPUT2(a, b) a, b + +struct paravirt_patch_site; +#ifdef CONFIG_PARAVIRT +void apply_paravirt(struct paravirt_patch_site *start, + struct paravirt_patch_site *end); +#else +static inline void apply_paravirt(struct paravirt_patch_site *start, + struct paravirt_patch_site *end) +{} +#define __parainstructions NULL +#define __parainstructions_end NULL +#endif + +extern void add_nops(void *insns, unsigned int len); + +/* + * Clear and restore the kernel write-protection flag on the local CPU. + * Allows the kernel to edit read-only pages. + * Side-effect: any interrupt handler running between save and restore will have + * the ability to write to read-only pages. + * + * Warning: + * Code patching in the UP case is safe if NMIs and MCE handlers are stopped and + * no thread can be preempted in the instructions being modified (no iret to an + * invalid instruction possible) or if the instructions are changed from a + * consistent state to another consistent state atomically. + * More care must be taken when modifying code in the SMP case because of + * Intel's errata. + * On the local CPU you need to be protected again NMI or MCE handlers seeing an + * inconsistent instruction while you patch. + * The _early version expects the memory to already be RW. + */ + +extern void *text_poke(void *addr, const void *opcode, size_t len); +extern void *text_poke_early(void *addr, const void *opcode, size_t len); + +#endif /* _ASM_X86_ALTERNATIVE_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/amd_iommu.h b/libdde-linux26/contrib/arch/x86/include/asm/amd_iommu.h new file mode 100644 index 00000000..f7123443 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/amd_iommu.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. + * Author: Joerg Roedel + * Leo Duran + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _ASM_X86_AMD_IOMMU_H +#define _ASM_X86_AMD_IOMMU_H + +#include + +#ifdef CONFIG_AMD_IOMMU +extern int amd_iommu_init(void); +extern int amd_iommu_init_dma_ops(void); +extern void amd_iommu_detect(void); +extern irqreturn_t amd_iommu_int_handler(int irq, void *data); +#else +static inline int amd_iommu_init(void) { return -ENODEV; } +static inline void amd_iommu_detect(void) { } +#endif + +#endif /* _ASM_X86_AMD_IOMMU_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/amd_iommu_types.h b/libdde-linux26/contrib/arch/x86/include/asm/amd_iommu_types.h new file mode 100644 index 00000000..95c8cd9d --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/amd_iommu_types.h @@ -0,0 +1,427 @@ +/* + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. + * Author: Joerg Roedel + * Leo Duran + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _ASM_X86_AMD_IOMMU_TYPES_H +#define _ASM_X86_AMD_IOMMU_TYPES_H + +#include +#include +#include + +/* + * some size calculation constants + */ +#define DEV_TABLE_ENTRY_SIZE 32 +#define ALIAS_TABLE_ENTRY_SIZE 2 +#define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) + +/* Length of the MMIO region for the AMD IOMMU */ +#define MMIO_REGION_LENGTH 0x4000 + +/* Capability offsets used by the driver */ +#define MMIO_CAP_HDR_OFFSET 0x00 +#define MMIO_RANGE_OFFSET 0x0c +#define MMIO_MISC_OFFSET 0x10 + +/* Masks, shifts and macros to parse the device range capability */ +#define MMIO_RANGE_LD_MASK 0xff000000 +#define MMIO_RANGE_FD_MASK 0x00ff0000 +#define MMIO_RANGE_BUS_MASK 0x0000ff00 +#define MMIO_RANGE_LD_SHIFT 24 +#define MMIO_RANGE_FD_SHIFT 16 +#define MMIO_RANGE_BUS_SHIFT 8 +#define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) +#define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) +#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) +#define MMIO_MSI_NUM(x) ((x) & 0x1f) + +/* Flag masks for the AMD IOMMU exclusion range */ +#define MMIO_EXCL_ENABLE_MASK 0x01ULL +#define MMIO_EXCL_ALLOW_MASK 0x02ULL + +/* Used offsets into the MMIO space */ +#define MMIO_DEV_TABLE_OFFSET 0x0000 +#define MMIO_CMD_BUF_OFFSET 0x0008 +#define MMIO_EVT_BUF_OFFSET 0x0010 +#define MMIO_CONTROL_OFFSET 0x0018 +#define MMIO_EXCL_BASE_OFFSET 0x0020 +#define MMIO_EXCL_LIMIT_OFFSET 0x0028 +#define MMIO_CMD_HEAD_OFFSET 0x2000 +#define MMIO_CMD_TAIL_OFFSET 0x2008 +#define MMIO_EVT_HEAD_OFFSET 0x2010 +#define MMIO_EVT_TAIL_OFFSET 0x2018 +#define MMIO_STATUS_OFFSET 0x2020 + +/* MMIO status bits */ +#define MMIO_STATUS_COM_WAIT_INT_MASK 0x04 + +/* event logging constants */ +#define EVENT_ENTRY_SIZE 0x10 +#define EVENT_TYPE_SHIFT 28 +#define EVENT_TYPE_MASK 0xf +#define EVENT_TYPE_ILL_DEV 0x1 +#define EVENT_TYPE_IO_FAULT 0x2 +#define EVENT_TYPE_DEV_TAB_ERR 0x3 +#define EVENT_TYPE_PAGE_TAB_ERR 0x4 +#define EVENT_TYPE_ILL_CMD 0x5 +#define EVENT_TYPE_CMD_HARD_ERR 0x6 +#define EVENT_TYPE_IOTLB_INV_TO 0x7 +#define EVENT_TYPE_INV_DEV_REQ 0x8 +#define EVENT_DEVID_MASK 0xffff +#define EVENT_DEVID_SHIFT 0 +#define EVENT_DOMID_MASK 0xffff +#define EVENT_DOMID_SHIFT 0 +#define EVENT_FLAGS_MASK 0xfff +#define EVENT_FLAGS_SHIFT 0x10 + +/* feature control bits */ +#define CONTROL_IOMMU_EN 0x00ULL +#define CONTROL_HT_TUN_EN 0x01ULL +#define CONTROL_EVT_LOG_EN 0x02ULL +#define CONTROL_EVT_INT_EN 0x03ULL +#define CONTROL_COMWAIT_EN 0x04ULL +#define CONTROL_PASSPW_EN 0x08ULL +#define CONTROL_RESPASSPW_EN 0x09ULL +#define CONTROL_COHERENT_EN 0x0aULL +#define CONTROL_ISOC_EN 0x0bULL +#define CONTROL_CMDBUF_EN 0x0cULL +#define CONTROL_PPFLOG_EN 0x0dULL +#define CONTROL_PPFINT_EN 0x0eULL + +/* command specific defines */ +#define CMD_COMPL_WAIT 0x01 +#define CMD_INV_DEV_ENTRY 0x02 +#define CMD_INV_IOMMU_PAGES 0x03 + +#define CMD_COMPL_WAIT_STORE_MASK 0x01 +#define CMD_COMPL_WAIT_INT_MASK 0x02 +#define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 +#define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 + +#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL + +/* macros and definitions for device table entries */ +#define DEV_ENTRY_VALID 0x00 +#define DEV_ENTRY_TRANSLATION 0x01 +#define DEV_ENTRY_IR 0x3d +#define DEV_ENTRY_IW 0x3e +#define DEV_ENTRY_NO_PAGE_FAULT 0x62 +#define DEV_ENTRY_EX 0x67 +#define DEV_ENTRY_SYSMGT1 0x68 +#define DEV_ENTRY_SYSMGT2 0x69 +#define DEV_ENTRY_INIT_PASS 0xb8 +#define DEV_ENTRY_EINT_PASS 0xb9 +#define DEV_ENTRY_NMI_PASS 0xba +#define DEV_ENTRY_LINT0_PASS 0xbe +#define DEV_ENTRY_LINT1_PASS 0xbf +#define DEV_ENTRY_MODE_MASK 0x07 +#define DEV_ENTRY_MODE_SHIFT 0x09 + +/* constants to configure the command buffer */ +#define CMD_BUFFER_SIZE 8192 +#define CMD_BUFFER_ENTRIES 512 +#define MMIO_CMD_SIZE_SHIFT 56 +#define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) + +/* constants for event buffer handling */ +#define EVT_BUFFER_SIZE 8192 /* 512 entries */ +#define EVT_LEN_MASK (0x9ULL << 56) + +#define PAGE_MODE_1_LEVEL 0x01 +#define PAGE_MODE_2_LEVEL 0x02 +#define PAGE_MODE_3_LEVEL 0x03 + +#define IOMMU_PDE_NL_0 0x000ULL +#define IOMMU_PDE_NL_1 0x200ULL +#define IOMMU_PDE_NL_2 0x400ULL +#define IOMMU_PDE_NL_3 0x600ULL + +#define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL) +#define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL) +#define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL) + +#define IOMMU_MAP_SIZE_L1 (1ULL << 21) +#define IOMMU_MAP_SIZE_L2 (1ULL << 30) +#define IOMMU_MAP_SIZE_L3 (1ULL << 39) + +#define IOMMU_PTE_P (1ULL << 0) +#define IOMMU_PTE_TV (1ULL << 1) +#define IOMMU_PTE_U (1ULL << 59) +#define IOMMU_PTE_FC (1ULL << 60) +#define IOMMU_PTE_IR (1ULL << 61) +#define IOMMU_PTE_IW (1ULL << 62) + +#define IOMMU_L1_PDE(address) \ + ((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) +#define IOMMU_L2_PDE(address) \ + ((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) + +#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) +#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P) +#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK)) +#define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) + +#define IOMMU_PROT_MASK 0x03 +#define IOMMU_PROT_IR 0x01 +#define IOMMU_PROT_IW 0x02 + +/* IOMMU capabilities */ +#define IOMMU_CAP_IOTLB 24 +#define IOMMU_CAP_NPCACHE 26 + +#define MAX_DOMAIN_ID 65536 + +/* FIXME: move this macro to */ +#define PCI_BUS(x) (((x) >> 8) & 0xff) + +/* Protection domain flags */ +#define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ +#define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops + domain for an IOMMU */ + +/* + * This structure contains generic data for IOMMU protection domains + * independent of their use. + */ +struct protection_domain { + spinlock_t lock; /* mostly used to lock the page table*/ + u16 id; /* the domain id written to the device table */ + int mode; /* paging mode (0-6 levels) */ + u64 *pt_root; /* page table root pointer */ + unsigned long flags; /* flags to find out type of domain */ + unsigned dev_cnt; /* devices assigned to this domain */ + void *priv; /* private data */ +}; + +/* + * Data container for a dma_ops specific protection domain + */ +struct dma_ops_domain { + struct list_head list; + + /* generic protection domain information */ + struct protection_domain domain; + + /* size of the aperture for the mappings */ + unsigned long aperture_size; + + /* address we start to search for free addresses */ + unsigned long next_bit; + + /* address allocation bitmap */ + unsigned long *bitmap; + + /* + * Array of PTE pages for the aperture. In this array we save all the + * leaf pages of the domain page table used for the aperture. This way + * we don't need to walk the page table to find a specific PTE. We can + * just calculate its address in constant time. + */ + u64 **pte_pages; + + /* This will be set to true when TLB needs to be flushed */ + bool need_flush; + + /* + * if this is a preallocated domain, keep the device for which it was + * preallocated in this variable + */ + u16 target_dev; +}; + +/* + * Structure where we save information about one hardware AMD IOMMU in the + * system. + */ +struct amd_iommu { + struct list_head list; + + /* locks the accesses to the hardware */ + spinlock_t lock; + + /* Pointer to PCI device of this IOMMU */ + struct pci_dev *dev; + + /* physical address of MMIO space */ + u64 mmio_phys; + /* virtual address of MMIO space */ + u8 *mmio_base; + + /* capabilities of that IOMMU read from ACPI */ + u32 cap; + + /* + * Capability pointer. There could be more than one IOMMU per PCI + * device function if there are more than one AMD IOMMU capability + * pointers. + */ + u16 cap_ptr; + + /* pci domain of this IOMMU */ + u16 pci_seg; + + /* first device this IOMMU handles. read from PCI */ + u16 first_device; + /* last device this IOMMU handles. read from PCI */ + u16 last_device; + + /* start of exclusion range of that IOMMU */ + u64 exclusion_start; + /* length of exclusion range of that IOMMU */ + u64 exclusion_length; + + /* command buffer virtual address */ + u8 *cmd_buf; + /* size of command buffer */ + u32 cmd_buf_size; + + /* size of event buffer */ + u32 evt_buf_size; + /* event buffer virtual address */ + u8 *evt_buf; + /* MSI number for event interrupt */ + u16 evt_msi_num; + + /* true if interrupts for this IOMMU are already enabled */ + bool int_enabled; + + /* if one, we need to send a completion wait command */ + bool need_sync; + + /* default dma_ops domain for that IOMMU */ + struct dma_ops_domain *default_dom; +}; + +/* + * List with all IOMMUs in the system. This list is not locked because it is + * only written and read at driver initialization or suspend time + */ +extern struct list_head amd_iommu_list; + +/* + * Structure defining one entry in the device table + */ +struct dev_table_entry { + u32 data[8]; +}; + +/* + * One entry for unity mappings parsed out of the ACPI table. + */ +struct unity_map_entry { + struct list_head list; + + /* starting device id this entry is used for (including) */ + u16 devid_start; + /* end device id this entry is used for (including) */ + u16 devid_end; + + /* start address to unity map (including) */ + u64 address_start; + /* end address to unity map (including) */ + u64 address_end; + + /* required protection */ + int prot; +}; + +/* + * List of all unity mappings. It is not locked because as runtime it is only + * read. It is created at ACPI table parsing time. + */ +extern struct list_head amd_iommu_unity_map; + +/* + * Data structures for device handling + */ + +/* + * Device table used by hardware. Read and write accesses by software are + * locked with the amd_iommu_pd_table lock. + */ +extern struct dev_table_entry *amd_iommu_dev_table; + +/* + * Alias table to find requestor ids to device ids. Not locked because only + * read on runtime. + */ +extern u16 *amd_iommu_alias_table; + +/* + * Reverse lookup table to find the IOMMU which translates a specific device. + */ +extern struct amd_iommu **amd_iommu_rlookup_table; + +/* size of the dma_ops aperture as power of 2 */ +extern unsigned amd_iommu_aperture_order; + +/* largest PCI device id we expect translation requests for */ +extern u16 amd_iommu_last_bdf; + +/* data structures for protection domain handling */ +extern struct protection_domain **amd_iommu_pd_table; + +/* allocation bitmap for domain ids */ +extern unsigned long *amd_iommu_pd_alloc_bitmap; + +/* will be 1 if device isolation is enabled */ +extern bool amd_iommu_isolate; + +/* + * If true, the addresses will be flushed on unmap time, not when + * they are reused + */ +extern bool amd_iommu_unmap_flush; + +/* takes bus and device/function and returns the device id + * FIXME: should that be in generic PCI code? */ +static inline u16 calc_devid(u8 bus, u8 devfn) +{ + return (((u16)bus) << 8) | devfn; +} + +#ifdef CONFIG_AMD_IOMMU_STATS + +struct __iommu_counter { + char *name; + struct dentry *dent; + u64 value; +}; + +#define DECLARE_STATS_COUNTER(nm) \ + static struct __iommu_counter nm = { \ + .name = #nm, \ + } + +#define INC_STATS_COUNTER(name) name.value += 1 +#define ADD_STATS_COUNTER(name, x) name.value += (x) +#define SUB_STATS_COUNTER(name, x) name.value -= (x) + +#else /* CONFIG_AMD_IOMMU_STATS */ + +#define DECLARE_STATS_COUNTER(name) +#define INC_STATS_COUNTER(name) +#define ADD_STATS_COUNTER(name, x) +#define SUB_STATS_COUNTER(name, x) + +static inline void amd_iommu_stats_init(void) { } + +#endif /* CONFIG_AMD_IOMMU_STATS */ + +#endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/apic.h b/libdde-linux26/contrib/arch/x86/include/asm/apic.h new file mode 100644 index 00000000..ab1d51a8 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/apic.h @@ -0,0 +1,199 @@ +#ifndef _ASM_X86_APIC_H +#define _ASM_X86_APIC_H + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define ARCH_APICTIMER_STOPS_ON_C3 1 + +/* + * Debugging macros + */ +#define APIC_QUIET 0 +#define APIC_VERBOSE 1 +#define APIC_DEBUG 2 + +/* + * Define the default level of output to be very little + * This can be turned up by using apic=verbose for more + * information and apic=debug for _lots_ of information. + * apic_verbosity is defined in apic.c + */ +#define apic_printk(v, s, a...) do { \ + if ((v) <= apic_verbosity) \ + printk(s, ##a); \ + } while (0) + + +extern void generic_apic_probe(void); + +#ifdef CONFIG_X86_LOCAL_APIC + +extern unsigned int apic_verbosity; +extern int local_apic_timer_c2_ok; + +extern int disable_apic; +/* + * Basic functions accessing APICs. + */ +#ifdef CONFIG_PARAVIRT +#include +#else +#define setup_boot_clock setup_boot_APIC_clock +#define setup_secondary_clock setup_secondary_APIC_clock +#endif + +extern int is_vsmp_box(void); +extern void xapic_wait_icr_idle(void); +extern u32 safe_xapic_wait_icr_idle(void); +extern void xapic_icr_write(u32, u32); +extern int setup_profiling_timer(unsigned int); + +static inline void native_apic_mem_write(u32 reg, u32 v) +{ + volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); + + alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, + ASM_OUTPUT2("=r" (v), "=m" (*addr)), + ASM_OUTPUT2("0" (v), "m" (*addr))); +} + +static inline u32 native_apic_mem_read(u32 reg) +{ + return *((volatile u32 *)(APIC_BASE + reg)); +} + +static inline void native_apic_msr_write(u32 reg, u32 v) +{ + if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || + reg == APIC_LVR) + return; + + wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); +} + +static inline u32 native_apic_msr_read(u32 reg) +{ + u32 low, high; + + if (reg == APIC_DFR) + return -1; + + rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); + return low; +} + +#ifndef CONFIG_X86_32 +extern int x2apic; +extern void check_x2apic(void); +extern void enable_x2apic(void); +extern void enable_IR_x2apic(void); +extern void x2apic_icr_write(u32 low, u32 id); +static inline int x2apic_enabled(void) +{ + int msr, msr2; + + if (!cpu_has_x2apic) + return 0; + + rdmsr(MSR_IA32_APICBASE, msr, msr2); + if (msr & X2APIC_ENABLE) + return 1; + return 0; +} +#else +#define x2apic_enabled() 0 +#endif + +struct apic_ops { + u32 (*read)(u32 reg); + void (*write)(u32 reg, u32 v); + u64 (*icr_read)(void); + void (*icr_write)(u32 low, u32 high); + void (*wait_icr_idle)(void); + u32 (*safe_wait_icr_idle)(void); +}; + +extern struct apic_ops *apic_ops; + +#define apic_read (apic_ops->read) +#define apic_write (apic_ops->write) +#define apic_icr_read (apic_ops->icr_read) +#define apic_icr_write (apic_ops->icr_write) +#define apic_wait_icr_idle (apic_ops->wait_icr_idle) +#define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle) + +extern int get_physical_broadcast(void); + +#ifdef CONFIG_X86_64 +static inline void ack_x2APIC_irq(void) +{ + /* Docs say use 0 for future compatibility */ + native_apic_msr_write(APIC_EOI, 0); +} +#endif + + +static inline void ack_APIC_irq(void) +{ + /* + * ack_APIC_irq() actually gets compiled as a single instruction + * ... yummie. + */ + + /* Docs say use 0 for future compatibility */ + apic_write(APIC_EOI, 0); +} + +extern int lapic_get_maxlvt(void); +extern void clear_local_APIC(void); +extern void connect_bsp_APIC(void); +extern void disconnect_bsp_APIC(int virt_wire_setup); +extern void disable_local_APIC(void); +extern void lapic_shutdown(void); +extern int verify_local_APIC(void); +extern void cache_APIC_registers(void); +extern void sync_Arb_IDs(void); +extern void init_bsp_APIC(void); +extern void setup_local_APIC(void); +extern void end_local_APIC_setup(void); +extern void init_apic_mappings(void); +extern void setup_boot_APIC_clock(void); +extern void setup_secondary_APIC_clock(void); +extern int APIC_init_uniprocessor(void); +extern void enable_NMI_through_LVT0(void); + +/* + * On 32bit this is mach-xxx local + */ +#ifdef CONFIG_X86_64 +extern void early_init_lapic_mapping(void); +extern int apic_is_clustered_box(void); +#else +static inline int apic_is_clustered_box(void) +{ + return 0; +} +#endif + +extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); +extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); + + +#else /* !CONFIG_X86_LOCAL_APIC */ +static inline void lapic_shutdown(void) { } +#define local_apic_timer_c2_ok 1 +static inline void init_apic_mappings(void) { } +static inline void disable_local_APIC(void) { } + +#endif /* !CONFIG_X86_LOCAL_APIC */ + +#endif /* _ASM_X86_APIC_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/apicdef.h b/libdde-linux26/contrib/arch/x86/include/asm/apicdef.h new file mode 100644 index 00000000..63134e31 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/apicdef.h @@ -0,0 +1,417 @@ +#ifndef _ASM_X86_APICDEF_H +#define _ASM_X86_APICDEF_H + +/* + * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) + * + * Alan Cox , 1995. + * Ingo Molnar , 1999, 2000 + */ + +#define APIC_DEFAULT_PHYS_BASE 0xfee00000 + +#define APIC_ID 0x20 + +#define APIC_LVR 0x30 +#define APIC_LVR_MASK 0xFF00FF +#define GET_APIC_VERSION(x) ((x) & 0xFFu) +#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) +#ifdef CONFIG_X86_32 +# define APIC_INTEGRATED(x) ((x) & 0xF0u) +#else +# define APIC_INTEGRATED(x) (1) +#endif +#define APIC_XAPIC(x) ((x) >= 0x14) +#define APIC_TASKPRI 0x80 +#define APIC_TPRI_MASK 0xFFu +#define APIC_ARBPRI 0x90 +#define APIC_ARBPRI_MASK 0xFFu +#define APIC_PROCPRI 0xA0 +#define APIC_EOI 0xB0 +#define APIC_EIO_ACK 0x0 +#define APIC_RRR 0xC0 +#define APIC_LDR 0xD0 +#define APIC_LDR_MASK (0xFFu << 24) +#define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) +#define SET_APIC_LOGICAL_ID(x) (((x) << 24)) +#define APIC_ALL_CPUS 0xFFu +#define APIC_DFR 0xE0 +#define APIC_DFR_CLUSTER 0x0FFFFFFFul +#define APIC_DFR_FLAT 0xFFFFFFFFul +#define APIC_SPIV 0xF0 +#define APIC_SPIV_FOCUS_DISABLED (1 << 9) +#define APIC_SPIV_APIC_ENABLED (1 << 8) +#define APIC_ISR 0x100 +#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ +#define APIC_TMR 0x180 +#define APIC_IRR 0x200 +#define APIC_ESR 0x280 +#define APIC_ESR_SEND_CS 0x00001 +#define APIC_ESR_RECV_CS 0x00002 +#define APIC_ESR_SEND_ACC 0x00004 +#define APIC_ESR_RECV_ACC 0x00008 +#define APIC_ESR_SENDILL 0x00020 +#define APIC_ESR_RECVILL 0x00040 +#define APIC_ESR_ILLREGA 0x00080 +#define APIC_ICR 0x300 +#define APIC_DEST_SELF 0x40000 +#define APIC_DEST_ALLINC 0x80000 +#define APIC_DEST_ALLBUT 0xC0000 +#define APIC_ICR_RR_MASK 0x30000 +#define APIC_ICR_RR_INVALID 0x00000 +#define APIC_ICR_RR_INPROG 0x10000 +#define APIC_ICR_RR_VALID 0x20000 +#define APIC_INT_LEVELTRIG 0x08000 +#define APIC_INT_ASSERT 0x04000 +#define APIC_ICR_BUSY 0x01000 +#define APIC_DEST_LOGICAL 0x00800 +#define APIC_DEST_PHYSICAL 0x00000 +#define APIC_DM_FIXED 0x00000 +#define APIC_DM_LOWEST 0x00100 +#define APIC_DM_SMI 0x00200 +#define APIC_DM_REMRD 0x00300 +#define APIC_DM_NMI 0x00400 +#define APIC_DM_INIT 0x00500 +#define APIC_DM_STARTUP 0x00600 +#define APIC_DM_EXTINT 0x00700 +#define APIC_VECTOR_MASK 0x000FF +#define APIC_ICR2 0x310 +#define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) +#define SET_APIC_DEST_FIELD(x) ((x) << 24) +#define APIC_LVTT 0x320 +#define APIC_LVTTHMR 0x330 +#define APIC_LVTPC 0x340 +#define APIC_LVT0 0x350 +#define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) +#define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) +#define SET_APIC_TIMER_BASE(x) (((x) << 18)) +#define APIC_TIMER_BASE_CLKIN 0x0 +#define APIC_TIMER_BASE_TMBASE 0x1 +#define APIC_TIMER_BASE_DIV 0x2 +#define APIC_LVT_TIMER_PERIODIC (1 << 17) +#define APIC_LVT_MASKED (1 << 16) +#define APIC_LVT_LEVEL_TRIGGER (1 << 15) +#define APIC_LVT_REMOTE_IRR (1 << 14) +#define APIC_INPUT_POLARITY (1 << 13) +#define APIC_SEND_PENDING (1 << 12) +#define APIC_MODE_MASK 0x700 +#define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) +#define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) +#define APIC_MODE_FIXED 0x0 +#define APIC_MODE_NMI 0x4 +#define APIC_MODE_EXTINT 0x7 +#define APIC_LVT1 0x360 +#define APIC_LVTERR 0x370 +#define APIC_TMICT 0x380 +#define APIC_TMCCT 0x390 +#define APIC_TDCR 0x3E0 +#define APIC_SELF_IPI 0x3F0 +#define APIC_TDR_DIV_TMBASE (1 << 2) +#define APIC_TDR_DIV_1 0xB +#define APIC_TDR_DIV_2 0x0 +#define APIC_TDR_DIV_4 0x1 +#define APIC_TDR_DIV_8 0x2 +#define APIC_TDR_DIV_16 0x3 +#define APIC_TDR_DIV_32 0x8 +#define APIC_TDR_DIV_64 0x9 +#define APIC_TDR_DIV_128 0xA +#define APIC_EILVT0 0x500 +#define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ +#define APIC_EILVT_NR_AMD_10H 4 +#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) +#define APIC_EILVT_MSG_FIX 0x0 +#define APIC_EILVT_MSG_SMI 0x2 +#define APIC_EILVT_MSG_NMI 0x4 +#define APIC_EILVT_MSG_EXT 0x7 +#define APIC_EILVT_MASKED (1 << 16) +#define APIC_EILVT1 0x510 +#define APIC_EILVT2 0x520 +#define APIC_EILVT3 0x530 + +#define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) +#define APIC_BASE_MSR 0x800 +#define X2APIC_ENABLE (1UL << 10) + +#ifdef CONFIG_X86_32 +# define MAX_IO_APICS 64 +#else +# define MAX_IO_APICS 128 +# define MAX_LOCAL_APIC 32768 +#endif + +/* + * All x86-64 systems are xAPIC compatible. + * In the following, "apicid" is a physical APIC ID. + */ +#define XAPIC_DEST_CPUS_SHIFT 4 +#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) +#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) +#define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) +#define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) +#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) +#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) + +/* + * the local APIC register structure, memory mapped. Not terribly well + * tested, but we might eventually use this one in the future - the + * problem why we cannot use it right now is the P5 APIC, it has an + * errata which cannot take 8-bit reads and writes, only 32-bit ones ... + */ +#define u32 unsigned int + +struct local_apic { + +/*000*/ struct { u32 __reserved[4]; } __reserved_01; + +/*010*/ struct { u32 __reserved[4]; } __reserved_02; + +/*020*/ struct { /* APIC ID Register */ + u32 __reserved_1 : 24, + phys_apic_id : 4, + __reserved_2 : 4; + u32 __reserved[3]; + } id; + +/*030*/ const + struct { /* APIC Version Register */ + u32 version : 8, + __reserved_1 : 8, + max_lvt : 8, + __reserved_2 : 8; + u32 __reserved[3]; + } version; + +/*040*/ struct { u32 __reserved[4]; } __reserved_03; + +/*050*/ struct { u32 __reserved[4]; } __reserved_04; + +/*060*/ struct { u32 __reserved[4]; } __reserved_05; + +/*070*/ struct { u32 __reserved[4]; } __reserved_06; + +/*080*/ struct { /* Task Priority Register */ + u32 priority : 8, + __reserved_1 : 24; + u32 __reserved_2[3]; + } tpr; + +/*090*/ const + struct { /* Arbitration Priority Register */ + u32 priority : 8, + __reserved_1 : 24; + u32 __reserved_2[3]; + } apr; + +/*0A0*/ const + struct { /* Processor Priority Register */ + u32 priority : 8, + __reserved_1 : 24; + u32 __reserved_2[3]; + } ppr; + +/*0B0*/ struct { /* End Of Interrupt Register */ + u32 eoi; + u32 __reserved[3]; + } eoi; + +/*0C0*/ struct { u32 __reserved[4]; } __reserved_07; + +/*0D0*/ struct { /* Logical Destination Register */ + u32 __reserved_1 : 24, + logical_dest : 8; + u32 __reserved_2[3]; + } ldr; + +/*0E0*/ struct { /* Destination Format Register */ + u32 __reserved_1 : 28, + model : 4; + u32 __reserved_2[3]; + } dfr; + +/*0F0*/ struct { /* Spurious Interrupt Vector Register */ + u32 spurious_vector : 8, + apic_enabled : 1, + focus_cpu : 1, + __reserved_2 : 22; + u32 __reserved_3[3]; + } svr; + +/*100*/ struct { /* In Service Register */ +/*170*/ u32 bitfield; + u32 __reserved[3]; + } isr [8]; + +/*180*/ struct { /* Trigger Mode Register */ +/*1F0*/ u32 bitfield; + u32 __reserved[3]; + } tmr [8]; + +/*200*/ struct { /* Interrupt Request Register */ +/*270*/ u32 bitfield; + u32 __reserved[3]; + } irr [8]; + +/*280*/ union { /* Error Status Register */ + struct { + u32 send_cs_error : 1, + receive_cs_error : 1, + send_accept_error : 1, + receive_accept_error : 1, + __reserved_1 : 1, + send_illegal_vector : 1, + receive_illegal_vector : 1, + illegal_register_address : 1, + __reserved_2 : 24; + u32 __reserved_3[3]; + } error_bits; + struct { + u32 errors; + u32 __reserved_3[3]; + } all_errors; + } esr; + +/*290*/ struct { u32 __reserved[4]; } __reserved_08; + +/*2A0*/ struct { u32 __reserved[4]; } __reserved_09; + +/*2B0*/ struct { u32 __reserved[4]; } __reserved_10; + +/*2C0*/ struct { u32 __reserved[4]; } __reserved_11; + +/*2D0*/ struct { u32 __reserved[4]; } __reserved_12; + +/*2E0*/ struct { u32 __reserved[4]; } __reserved_13; + +/*2F0*/ struct { u32 __reserved[4]; } __reserved_14; + +/*300*/ struct { /* Interrupt Command Register 1 */ + u32 vector : 8, + delivery_mode : 3, + destination_mode : 1, + delivery_status : 1, + __reserved_1 : 1, + level : 1, + trigger : 1, + __reserved_2 : 2, + shorthand : 2, + __reserved_3 : 12; + u32 __reserved_4[3]; + } icr1; + +/*310*/ struct { /* Interrupt Command Register 2 */ + union { + u32 __reserved_1 : 24, + phys_dest : 4, + __reserved_2 : 4; + u32 __reserved_3 : 24, + logical_dest : 8; + } dest; + u32 __reserved_4[3]; + } icr2; + +/*320*/ struct { /* LVT - Timer */ + u32 vector : 8, + __reserved_1 : 4, + delivery_status : 1, + __reserved_2 : 3, + mask : 1, + timer_mode : 1, + __reserved_3 : 14; + u32 __reserved_4[3]; + } lvt_timer; + +/*330*/ struct { /* LVT - Thermal Sensor */ + u32 vector : 8, + delivery_mode : 3, + __reserved_1 : 1, + delivery_status : 1, + __reserved_2 : 3, + mask : 1, + __reserved_3 : 15; + u32 __reserved_4[3]; + } lvt_thermal; + +/*340*/ struct { /* LVT - Performance Counter */ + u32 vector : 8, + delivery_mode : 3, + __reserved_1 : 1, + delivery_status : 1, + __reserved_2 : 3, + mask : 1, + __reserved_3 : 15; + u32 __reserved_4[3]; + } lvt_pc; + +/*350*/ struct { /* LVT - LINT0 */ + u32 vector : 8, + delivery_mode : 3, + __reserved_1 : 1, + delivery_status : 1, + polarity : 1, + remote_irr : 1, + trigger : 1, + mask : 1, + __reserved_2 : 15; + u32 __reserved_3[3]; + } lvt_lint0; + +/*360*/ struct { /* LVT - LINT1 */ + u32 vector : 8, + delivery_mode : 3, + __reserved_1 : 1, + delivery_status : 1, + polarity : 1, + remote_irr : 1, + trigger : 1, + mask : 1, + __reserved_2 : 15; + u32 __reserved_3[3]; + } lvt_lint1; + +/*370*/ struct { /* LVT - Error */ + u32 vector : 8, + __reserved_1 : 4, + delivery_status : 1, + __reserved_2 : 3, + mask : 1, + __reserved_3 : 15; + u32 __reserved_4[3]; + } lvt_error; + +/*380*/ struct { /* Timer Initial Count Register */ + u32 initial_count; + u32 __reserved_2[3]; + } timer_icr; + +/*390*/ const + struct { /* Timer Current Count Register */ + u32 curr_count; + u32 __reserved_2[3]; + } timer_ccr; + +/*3A0*/ struct { u32 __reserved[4]; } __reserved_16; + +/*3B0*/ struct { u32 __reserved[4]; } __reserved_17; + +/*3C0*/ struct { u32 __reserved[4]; } __reserved_18; + +/*3D0*/ struct { u32 __reserved[4]; } __reserved_19; + +/*3E0*/ struct { /* Timer Divide Configuration Register */ + u32 divisor : 4, + __reserved_1 : 28; + u32 __reserved_2[3]; + } timer_dcr; + +/*3F0*/ struct { u32 __reserved[4]; } __reserved_20; + +} __attribute__ ((packed)); + +#undef u32 + +#ifdef CONFIG_X86_32 + #define BAD_APICID 0xFFu +#else + #define BAD_APICID 0xFFFFu +#endif +#endif /* _ASM_X86_APICDEF_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/arch_hooks.h b/libdde-linux26/contrib/arch/x86/include/asm/arch_hooks.h new file mode 100644 index 00000000..cbd49578 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/arch_hooks.h @@ -0,0 +1,26 @@ +#ifndef _ASM_X86_ARCH_HOOKS_H +#define _ASM_X86_ARCH_HOOKS_H + +#include + +/* + * linux/include/asm/arch_hooks.h + * + * define the architecture specific hooks + */ + +/* these aren't arch hooks, they are generic routines + * that can be used by the hooks */ +extern void init_ISA_irqs(void); +extern irqreturn_t timer_interrupt(int irq, void *dev_id); + +/* these are the defined hooks */ +extern void intr_init_hook(void); +extern void pre_intr_init_hook(void); +extern void pre_setup_arch_hook(void); +extern void trap_init_hook(void); +extern void pre_time_init_hook(void); +extern void time_init_hook(void); +extern void mca_nmi_hook(void); + +#endif /* _ASM_X86_ARCH_HOOKS_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/asm.h b/libdde-linux26/contrib/arch/x86/include/asm/asm.h new file mode 100644 index 00000000..56be78f5 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/asm.h @@ -0,0 +1,47 @@ +#ifndef _ASM_X86_ASM_H +#define _ASM_X86_ASM_H + +#ifdef __ASSEMBLY__ +# define __ASM_FORM(x) x +# define __ASM_EX_SEC .section __ex_table +#else +# define __ASM_FORM(x) " " #x " " +# define __ASM_EX_SEC " .section __ex_table,\"a\"\n" +#endif + +#ifdef CONFIG_X86_32 +# define __ASM_SEL(a,b) __ASM_FORM(a) +#else +# define __ASM_SEL(a,b) __ASM_FORM(b) +#endif + +#define __ASM_SIZE(inst) __ASM_SEL(inst##l, inst##q) +#define __ASM_REG(reg) __ASM_SEL(e##reg, r##reg) + +#define _ASM_PTR __ASM_SEL(.long, .quad) +#define _ASM_ALIGN __ASM_SEL(.balign 4, .balign 8) + +#define _ASM_MOV __ASM_SIZE(mov) +#define _ASM_INC __ASM_SIZE(inc) +#define _ASM_DEC __ASM_SIZE(dec) +#define _ASM_ADD __ASM_SIZE(add) +#define _ASM_SUB __ASM_SIZE(sub) +#define _ASM_XADD __ASM_SIZE(xadd) + +#define _ASM_AX __ASM_REG(ax) +#define _ASM_BX __ASM_REG(bx) +#define _ASM_CX __ASM_REG(cx) +#define _ASM_DX __ASM_REG(dx) +#define _ASM_SP __ASM_REG(sp) +#define _ASM_BP __ASM_REG(bp) +#define _ASM_SI __ASM_REG(si) +#define _ASM_DI __ASM_REG(di) + +/* Exception table entry */ +# define _ASM_EXTABLE(from,to) \ + __ASM_EX_SEC \ + _ASM_ALIGN "\n" \ + _ASM_PTR #from "," #to "\n" \ + " .previous\n" + +#endif /* _ASM_X86_ASM_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/atomic.h b/libdde-linux26/contrib/arch/x86/include/asm/atomic.h new file mode 100644 index 00000000..4e1b8873 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/atomic.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_X86_32 +# include "atomic_32.h" +#else +# include "atomic_64.h" +#endif diff --git a/libdde-linux26/contrib/arch/x86/include/asm/atomic_32.h b/libdde-linux26/contrib/arch/x86/include/asm/atomic_32.h new file mode 100644 index 00000000..85b46fba --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/atomic_32.h @@ -0,0 +1,251 @@ +#ifndef _ASM_X86_ATOMIC_32_H +#define _ASM_X86_ATOMIC_32_H + +#include +#include +#include +#include + +/* + * Atomic operations that C can't guarantee us. Useful for + * resource counting etc.. + */ + +#define ATOMIC_INIT(i) { (i) } + +/** + * atomic_read - read atomic variable + * @v: pointer of type atomic_t + * + * Atomically reads the value of @v. + */ +#define atomic_read(v) ((v)->counter) + +/** + * atomic_set - set atomic variable + * @v: pointer of type atomic_t + * @i: required value + * + * Atomically sets the value of @v to @i. + */ +#define atomic_set(v, i) (((v)->counter) = (i)) + +/** + * atomic_add - add integer to atomic variable + * @i: integer value to add + * @v: pointer of type atomic_t + * + * Atomically adds @i to @v. + */ +static inline void atomic_add(int i, atomic_t *v) +{ + asm volatile(LOCK_PREFIX "addl %1,%0" + : "+m" (v->counter) + : "ir" (i)); +} + +/** + * atomic_sub - subtract integer from atomic variable + * @i: integer value to subtract + * @v: pointer of type atomic_t + * + * Atomically subtracts @i from @v. + */ +static inline void atomic_sub(int i, atomic_t *v) +{ + asm volatile(LOCK_PREFIX "subl %1,%0" + : "+m" (v->counter) + : "ir" (i)); +} + +/** + * atomic_sub_and_test - subtract value from variable and test result + * @i: integer value to subtract + * @v: pointer of type atomic_t + * + * Atomically subtracts @i from @v and returns + * true if the result is zero, or false for all + * other cases. + */ +static inline int atomic_sub_and_test(int i, atomic_t *v) +{ + unsigned char c; + + asm volatile(LOCK_PREFIX "subl %2,%0; sete %1" + : "+m" (v->counter), "=qm" (c) + : "ir" (i) : "memory"); + return c; +} + +/** + * atomic_inc - increment atomic variable + * @v: pointer of type atomic_t + * + * Atomically increments @v by 1. + */ +static inline void atomic_inc(atomic_t *v) +{ + asm volatile(LOCK_PREFIX "incl %0" + : "+m" (v->counter)); +} + +/** + * atomic_dec - decrement atomic variable + * @v: pointer of type atomic_t + * + * Atomically decrements @v by 1. + */ +static inline void atomic_dec(atomic_t *v) +{ + asm volatile(LOCK_PREFIX "decl %0" + : "+m" (v->counter)); +} + +/** + * atomic_dec_and_test - decrement and test + * @v: pointer of type atomic_t + * + * Atomically decrements @v by 1 and + * returns true if the result is 0, or false for all other + * cases. + */ +static inline int atomic_dec_and_test(atomic_t *v) +{ + unsigned char c; + + asm volatile(LOCK_PREFIX "decl %0; sete %1" + : "+m" (v->counter), "=qm" (c) + : : "memory"); + return c != 0; +} + +/** + * atomic_inc_and_test - increment and test + * @v: pointer of type atomic_t + * + * Atomically increments @v by 1 + * and returns true if the result is zero, or false for all + * other cases. + */ +static inline int atomic_inc_and_test(atomic_t *v) +{ + unsigned char c; + + asm volatile(LOCK_PREFIX "incl %0; sete %1" + : "+m" (v->counter), "=qm" (c) + : : "memory"); + return c != 0; +} + +/** + * atomic_add_negative - add and test if negative + * @v: pointer of type atomic_t + * @i: integer value to add + * + * Atomically adds @i to @v and returns true + * if the result is negative, or false when + * result is greater than or equal to zero. + */ +static inline int atomic_add_negative(int i, atomic_t *v) +{ + unsigned char c; + + asm volatile(LOCK_PREFIX "addl %2,%0; sets %1" + : "+m" (v->counter), "=qm" (c) + : "ir" (i) : "memory"); + return c; +} + +/** + * atomic_add_return - add integer and return + * @v: pointer of type atomic_t + * @i: integer value to add + * + * Atomically adds @i to @v and returns @i + @v + */ +static inline int atomic_add_return(int i, atomic_t *v) +{ + int __i; +#ifdef CONFIG_M386 + unsigned long flags; + if (unlikely(boot_cpu_data.x86 <= 3)) + goto no_xadd; +#endif + /* Modern 486+ processor */ + __i = i; + asm volatile(LOCK_PREFIX "xaddl %0, %1" + : "+r" (i), "+m" (v->counter) + : : "memory"); + return i + __i; + +#ifdef CONFIG_M386 +no_xadd: /* Legacy 386 processor */ + local_irq_save(flags); + __i = atomic_read(v); + atomic_set(v, i + __i); + local_irq_restore(flags); + return i + __i; +#endif +} + +/** + * atomic_sub_return - subtract integer and return + * @v: pointer of type atomic_t + * @i: integer value to subtract + * + * Atomically subtracts @i from @v and returns @v - @i + */ +static inline int atomic_sub_return(int i, atomic_t *v) +{ + return atomic_add_return(-i, v); +} + +#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), (new))) + +/** + * atomic_add_unless - add unless the number is already a given value + * @v: pointer of type atomic_t + * @a: the amount to add to v... + * @u: ...unless v is equal to u. + * + * Atomically adds @a to @v, so long as @v was not already @u. + * Returns non-zero if @v was not @u, and zero otherwise. + */ +static inline int atomic_add_unless(atomic_t *v, int a, int u) +{ + int c, old; + c = atomic_read(v); + for (;;) { + if (unlikely(c == (u))) + break; + old = atomic_cmpxchg((v), c, c + (a)); + if (likely(old == c)) + break; + c = old; + } + return c != (u); +} + +#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) + +#define atomic_inc_return(v) (atomic_add_return(1, v)) +#define atomic_dec_return(v) (atomic_sub_return(1, v)) + +/* These are x86-specific, used by some header files */ +#define atomic_clear_mask(mask, addr) \ + asm volatile(LOCK_PREFIX "andl %0,%1" \ + : : "r" (~(mask)), "m" (*(addr)) : "memory") + +#define atomic_set_mask(mask, addr) \ + asm volatile(LOCK_PREFIX "orl %0,%1" \ + : : "r" (mask), "m" (*(addr)) : "memory") + +/* Atomic operations are already serializing on x86 */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +#include +#endif /* _ASM_X86_ATOMIC_32_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/atomic_64.h b/libdde-linux26/contrib/arch/x86/include/asm/atomic_64.h new file mode 100644 index 00000000..8c217319 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/atomic_64.h @@ -0,0 +1,459 @@ +#ifndef _ASM_X86_ATOMIC_64_H +#define _ASM_X86_ATOMIC_64_H + +#include +#include +#include + +/* + * Atomic operations that C can't guarantee us. Useful for + * resource counting etc.. + */ + +#define ATOMIC_INIT(i) { (i) } + +/** + * atomic_read - read atomic variable + * @v: pointer of type atomic_t + * + * Atomically reads the value of @v. + */ +#define atomic_read(v) ((v)->counter) + +/** + * atomic_set - set atomic variable + * @v: pointer of type atomic_t + * @i: required value + * + * Atomically sets the value of @v to @i. + */ +#define atomic_set(v, i) (((v)->counter) = (i)) + +/** + * atomic_add - add integer to atomic variable + * @i: integer value to add + * @v: pointer of type atomic_t + * + * Atomically adds @i to @v. + */ +static inline void atomic_add(int i, atomic_t *v) +{ + asm volatile(LOCK_PREFIX "addl %1,%0" + : "=m" (v->counter) + : "ir" (i), "m" (v->counter)); +} + +/** + * atomic_sub - subtract the atomic variable + * @i: integer value to subtract + * @v: pointer of type atomic_t + * + * Atomically subtracts @i from @v. + */ +static inline void atomic_sub(int i, atomic_t *v) +{ + asm volatile(LOCK_PREFIX "subl %1,%0" + : "=m" (v->counter) + : "ir" (i), "m" (v->counter)); +} + +/** + * atomic_sub_and_test - subtract value from variable and test result + * @i: integer value to subtract + * @v: pointer of type atomic_t + * + * Atomically subtracts @i from @v and returns + * true if the result is zero, or false for all + * other cases. + */ +static inline int atomic_sub_and_test(int i, atomic_t *v) +{ + unsigned char c; + + asm volatile(LOCK_PREFIX "subl %2,%0; sete %1" + : "=m" (v->counter), "=qm" (c) + : "ir" (i), "m" (v->counter) : "memory"); + return c; +} + +/** + * atomic_inc - increment atomic variable + * @v: pointer of type atomic_t + * + * Atomically increments @v by 1. + */ +static inline void atomic_inc(atomic_t *v) +{ + asm volatile(LOCK_PREFIX "incl %0" + : "=m" (v->counter) + : "m" (v->counter)); +} + +/** + * atomic_dec - decrement atomic variable + * @v: pointer of type atomic_t + * + * Atomically decrements @v by 1. + */ +static inline void atomic_dec(atomic_t *v) +{ + asm volatile(LOCK_PREFIX "decl %0" + : "=m" (v->counter) + : "m" (v->counter)); +} + +/** + * atomic_dec_and_test - decrement and test + * @v: pointer of type atomic_t + * + * Atomically decrements @v by 1 and + * returns true if the result is 0, or false for all other + * cases. + */ +static inline int atomic_dec_and_test(atomic_t *v) +{ + unsigned char c; + + asm volatile(LOCK_PREFIX "decl %0; sete %1" + : "=m" (v->counter), "=qm" (c) + : "m" (v->counter) : "memory"); + return c != 0; +} + +/** + * atomic_inc_and_test - increment and test + * @v: pointer of type atomic_t + * + * Atomically increments @v by 1 + * and returns true if the result is zero, or false for all + * other cases. + */ +static inline int atomic_inc_and_test(atomic_t *v) +{ + unsigned char c; + + asm volatile(LOCK_PREFIX "incl %0; sete %1" + : "=m" (v->counter), "=qm" (c) + : "m" (v->counter) : "memory"); + return c != 0; +} + +/** + * atomic_add_negative - add and test if negative + * @i: integer value to add + * @v: pointer of type atomic_t + * + * Atomically adds @i to @v and returns true + * if the result is negative, or false when + * result is greater than or equal to zero. + */ +static inline int atomic_add_negative(int i, atomic_t *v) +{ + unsigned char c; + + asm volatile(LOCK_PREFIX "addl %2,%0; sets %1" + : "=m" (v->counter), "=qm" (c) + : "ir" (i), "m" (v->counter) : "memory"); + return c; +} + +/** + * atomic_add_return - add and return + * @i: integer value to add + * @v: pointer of type atomic_t + * + * Atomically adds @i to @v and returns @i + @v + */ +static inline int atomic_add_return(int i, atomic_t *v) +{ + int __i = i; + asm volatile(LOCK_PREFIX "xaddl %0, %1" + : "+r" (i), "+m" (v->counter) + : : "memory"); + return i + __i; +} + +static inline int atomic_sub_return(int i, atomic_t *v) +{ + return atomic_add_return(-i, v); +} + +#define atomic_inc_return(v) (atomic_add_return(1, v)) +#define atomic_dec_return(v) (atomic_sub_return(1, v)) + +/* The 64-bit atomic type */ + +#define ATOMIC64_INIT(i) { (i) } + +/** + * atomic64_read - read atomic64 variable + * @v: pointer of type atomic64_t + * + * Atomically reads the value of @v. + * Doesn't imply a read memory barrier. + */ +#define atomic64_read(v) ((v)->counter) + +/** + * atomic64_set - set atomic64 variable + * @v: pointer to type atomic64_t + * @i: required value + * + * Atomically sets the value of @v to @i. + */ +#define atomic64_set(v, i) (((v)->counter) = (i)) + +/** + * atomic64_add - add integer to atomic64 variable + * @i: integer value to add + * @v: pointer to type atomic64_t + * + * Atomically adds @i to @v. + */ +static inline void atomic64_add(long i, atomic64_t *v) +{ + asm volatile(LOCK_PREFIX "addq %1,%0" + : "=m" (v->counter) + : "er" (i), "m" (v->counter)); +} + +/** + * atomic64_sub - subtract the atomic64 variable + * @i: integer value to subtract + * @v: pointer to type atomic64_t + * + * Atomically subtracts @i from @v. + */ +static inline void atomic64_sub(long i, atomic64_t *v) +{ + asm volatile(LOCK_PREFIX "subq %1,%0" + : "=m" (v->counter) + : "er" (i), "m" (v->counter)); +} + +/** + * atomic64_sub_and_test - subtract value from variable and test result + * @i: integer value to subtract + * @v: pointer to type atomic64_t + * + * Atomically subtracts @i from @v and returns + * true if the result is zero, or false for all + * other cases. + */ +static inline int atomic64_sub_and_test(long i, atomic64_t *v) +{ + unsigned char c; + + asm volatile(LOCK_PREFIX "subq %2,%0; sete %1" + : "=m" (v->counter), "=qm" (c) + : "er" (i), "m" (v->counter) : "memory"); + return c; +} + +/** + * atomic64_inc - increment atomic64 variable + * @v: pointer to type atomic64_t + * + * Atomically increments @v by 1. + */ +static inline void atomic64_inc(atomic64_t *v) +{ + asm volatile(LOCK_PREFIX "incq %0" + : "=m" (v->counter) + : "m" (v->counter)); +} + +/** + * atomic64_dec - decrement atomic64 variable + * @v: pointer to type atomic64_t + * + * Atomically decrements @v by 1. + */ +static inline void atomic64_dec(atomic64_t *v) +{ + asm volatile(LOCK_PREFIX "decq %0" + : "=m" (v->counter) + : "m" (v->counter)); +} + +/** + * atomic64_dec_and_test - decrement and test + * @v: pointer to type atomic64_t + * + * Atomically decrements @v by 1 and + * returns true if the result is 0, or false for all other + * cases. + */ +static inline int atomic64_dec_and_test(atomic64_t *v) +{ + unsigned char c; + + asm volatile(LOCK_PREFIX "decq %0; sete %1" + : "=m" (v->counter), "=qm" (c) + : "m" (v->counter) : "memory"); + return c != 0; +} + +/** + * atomic64_inc_and_test - increment and test + * @v: pointer to type atomic64_t + * + * Atomically increments @v by 1 + * and returns true if the result is zero, or false for all + * other cases. + */ +static inline int atomic64_inc_and_test(atomic64_t *v) +{ + unsigned char c; + + asm volatile(LOCK_PREFIX "incq %0; sete %1" + : "=m" (v->counter), "=qm" (c) + : "m" (v->counter) : "memory"); + return c != 0; +} + +/** + * atomic64_add_negative - add and test if negative + * @i: integer value to add + * @v: pointer to type atomic64_t + * + * Atomically adds @i to @v and returns true + * if the result is negative, or false when + * result is greater than or equal to zero. + */ +static inline int atomic64_add_negative(long i, atomic64_t *v) +{ + unsigned char c; + + asm volatile(LOCK_PREFIX "addq %2,%0; sets %1" + : "=m" (v->counter), "=qm" (c) + : "er" (i), "m" (v->counter) : "memory"); + return c; +} + +/** + * atomic64_add_return - add and return + * @i: integer value to add + * @v: pointer to type atomic64_t + * + * Atomically adds @i to @v and returns @i + @v + */ +static inline long atomic64_add_return(long i, atomic64_t *v) +{ + long __i = i; + asm volatile(LOCK_PREFIX "xaddq %0, %1;" + : "+r" (i), "+m" (v->counter) + : : "memory"); + return i + __i; +} + +static inline long atomic64_sub_return(long i, atomic64_t *v) +{ + return atomic64_add_return(-i, v); +} + +#define atomic64_inc_return(v) (atomic64_add_return(1, (v))) +#define atomic64_dec_return(v) (atomic64_sub_return(1, (v))) + +#define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new))) +#define atomic64_xchg(v, new) (xchg(&((v)->counter), new)) + +#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), (new))) + +/** + * atomic_add_unless - add unless the number is a given value + * @v: pointer of type atomic_t + * @a: the amount to add to v... + * @u: ...unless v is equal to u. + * + * Atomically adds @a to @v, so long as it was not @u. + * Returns non-zero if @v was not @u, and zero otherwise. + */ +static inline int atomic_add_unless(atomic_t *v, int a, int u) +{ + int c, old; + c = atomic_read(v); + for (;;) { + if (unlikely(c == (u))) + break; + old = atomic_cmpxchg((v), c, c + (a)); + if (likely(old == c)) + break; + c = old; + } + return c != (u); +} + +#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) + +/** + * atomic64_add_unless - add unless the number is a given value + * @v: pointer of type atomic64_t + * @a: the amount to add to v... + * @u: ...unless v is equal to u. + * + * Atomically adds @a to @v, so long as it was not @u. + * Returns non-zero if @v was not @u, and zero otherwise. + */ +static inline int atomic64_add_unless(atomic64_t *v, long a, long u) +{ + long c, old; + c = atomic64_read(v); + for (;;) { + if (unlikely(c == (u))) + break; + old = atomic64_cmpxchg((v), c, c + (a)); + if (likely(old == c)) + break; + c = old; + } + return c != (u); +} + +/** + * atomic_inc_short - increment of a short integer + * @v: pointer to type int + * + * Atomically adds 1 to @v + * Returns the new value of @u + */ +static inline short int atomic_inc_short(short int *v) +{ + asm(LOCK_PREFIX "addw $1, %0" : "+m" (*v)); + return *v; +} + +/** + * atomic_or_long - OR of two long integers + * @v1: pointer to type unsigned long + * @v2: pointer to type unsigned long + * + * Atomically ORs @v1 and @v2 + * Returns the result of the OR + */ +static inline void atomic_or_long(unsigned long *v1, unsigned long v2) +{ + asm(LOCK_PREFIX "orq %1, %0" : "+m" (*v1) : "r" (v2)); +} + +#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) + +/* These are x86-specific, used by some header files */ +#define atomic_clear_mask(mask, addr) \ + asm volatile(LOCK_PREFIX "andl %0,%1" \ + : : "r" (~(mask)), "m" (*(addr)) : "memory") + +#define atomic_set_mask(mask, addr) \ + asm volatile(LOCK_PREFIX "orl %0,%1" \ + : : "r" ((unsigned)(mask)), "m" (*(addr)) \ + : "memory") + +/* Atomic operations are already serializing on x86 */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +#include +#endif /* _ASM_X86_ATOMIC_64_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/auxvec.h b/libdde-linux26/contrib/arch/x86/include/asm/auxvec.h new file mode 100644 index 00000000..1316b4c3 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/auxvec.h @@ -0,0 +1,12 @@ +#ifndef _ASM_X86_AUXVEC_H +#define _ASM_X86_AUXVEC_H +/* + * Architecture-neutral AT_ values in 0-17, leave some room + * for more of them, start the x86-specific ones at 32. + */ +#ifdef __i386__ +#define AT_SYSINFO 32 +#endif +#define AT_SYSINFO_EHDR 33 + +#endif /* _ASM_X86_AUXVEC_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/bigsmp/apic.h b/libdde-linux26/contrib/arch/x86/include/asm/bigsmp/apic.h new file mode 100644 index 00000000..d8dd9f53 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/bigsmp/apic.h @@ -0,0 +1,155 @@ +#ifndef __ASM_MACH_APIC_H +#define __ASM_MACH_APIC_H + +#define xapic_phys_to_log_apicid(cpu) (per_cpu(x86_bios_cpu_apicid, cpu)) +#define esr_disable (1) + +static inline int apic_id_registered(void) +{ + return (1); +} + +static inline const cpumask_t *target_cpus(void) +{ +#ifdef CONFIG_SMP + return &cpu_online_map; +#else + return &cpumask_of_cpu(0); +#endif +} + +#undef APIC_DEST_LOGICAL +#define APIC_DEST_LOGICAL 0 +#define APIC_DFR_VALUE (APIC_DFR_FLAT) +#define INT_DELIVERY_MODE (dest_Fixed) +#define INT_DEST_MODE (0) /* phys delivery to target proc */ +#define NO_BALANCE_IRQ (0) + +static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) +{ + return (0); +} + +static inline unsigned long check_apicid_present(int bit) +{ + return (1); +} + +static inline unsigned long calculate_ldr(int cpu) +{ + unsigned long val, id; + val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; + id = xapic_phys_to_log_apicid(cpu); + val |= SET_APIC_LOGICAL_ID(id); + return val; +} + +/* + * Set up the logical destination ID. + * + * Intel recommends to set DFR, LDR and TPR before enabling + * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel + * document number 292116). So here it goes... + */ +static inline void init_apic_ldr(void) +{ + unsigned long val; + int cpu = smp_processor_id(); + + apic_write(APIC_DFR, APIC_DFR_VALUE); + val = calculate_ldr(cpu); + apic_write(APIC_LDR, val); +} + +static inline void setup_apic_routing(void) +{ + printk("Enabling APIC mode: %s. Using %d I/O APICs\n", + "Physflat", nr_ioapics); +} + +static inline int multi_timer_check(int apic, int irq) +{ + return (0); +} + +static inline int apicid_to_node(int logical_apicid) +{ + return apicid_2_node[hard_smp_processor_id()]; +} + +static inline int cpu_present_to_apicid(int mps_cpu) +{ + if (mps_cpu < nr_cpu_ids) + return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu); + + return BAD_APICID; +} + +static inline physid_mask_t apicid_to_cpu_present(int phys_apicid) +{ + return physid_mask_of_physid(phys_apicid); +} + +extern u8 cpu_2_logical_apicid[]; +/* Mapping from cpu number to logical apicid */ +static inline int cpu_to_logical_apicid(int cpu) +{ + if (cpu >= nr_cpu_ids) + return BAD_APICID; + return cpu_physical_id(cpu); +} + +static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map) +{ + /* For clustered we don't have a good way to do this yet - hack */ + return physids_promote(0xFFL); +} + +static inline void setup_portio_remap(void) +{ +} + +static inline void enable_apic_mode(void) +{ +} + +static inline int check_phys_apicid_present(int boot_cpu_physical_apicid) +{ + return (1); +} + +/* As we are using single CPU as destination, pick only one CPU here */ +static inline unsigned int cpu_mask_to_apicid(const cpumask_t *cpumask) +{ + int cpu; + int apicid; + + cpu = first_cpu(*cpumask); + apicid = cpu_to_logical_apicid(cpu); + return apicid; +} + +static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *cpumask, + const struct cpumask *andmask) +{ + int cpu; + + /* + * We're using fixed IRQ delivery, can only return one phys APIC ID. + * May as well be the first. + */ + for_each_cpu_and(cpu, cpumask, andmask) + if (cpumask_test_cpu(cpu, cpu_online_mask)) + break; + if (cpu < nr_cpu_ids) + return cpu_to_logical_apicid(cpu); + + return BAD_APICID; +} + +static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) +{ + return cpuid_apic >> index_msb; +} + +#endif /* __ASM_MACH_APIC_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/bigsmp/apicdef.h b/libdde-linux26/contrib/arch/x86/include/asm/bigsmp/apicdef.h new file mode 100644 index 00000000..392c3f5e --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/bigsmp/apicdef.h @@ -0,0 +1,13 @@ +#ifndef __ASM_MACH_APICDEF_H +#define __ASM_MACH_APICDEF_H + +#define APIC_ID_MASK (0xFF<<24) + +static inline unsigned get_apic_id(unsigned long x) +{ + return (((x)>>24)&0xFF); +} + +#define GET_APIC_ID(x) get_apic_id(x) + +#endif diff --git a/libdde-linux26/contrib/arch/x86/include/asm/bigsmp/ipi.h b/libdde-linux26/contrib/arch/x86/include/asm/bigsmp/ipi.h new file mode 100644 index 00000000..27fcd01b --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/bigsmp/ipi.h @@ -0,0 +1,22 @@ +#ifndef __ASM_MACH_IPI_H +#define __ASM_MACH_IPI_H + +void send_IPI_mask_sequence(const struct cpumask *mask, int vector); +void send_IPI_mask_allbutself(const struct cpumask *mask, int vector); + +static inline void send_IPI_mask(const struct cpumask *mask, int vector) +{ + send_IPI_mask_sequence(mask, vector); +} + +static inline void send_IPI_allbutself(int vector) +{ + send_IPI_mask_allbutself(cpu_online_mask, vector); +} + +static inline void send_IPI_all(int vector) +{ + send_IPI_mask(cpu_online_mask, vector); +} + +#endif /* __ASM_MACH_IPI_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/bios_ebda.h b/libdde-linux26/contrib/arch/x86/include/asm/bios_ebda.h new file mode 100644 index 00000000..3c752106 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/bios_ebda.h @@ -0,0 +1,36 @@ +#ifndef _ASM_X86_BIOS_EBDA_H +#define _ASM_X86_BIOS_EBDA_H + +#include + +/* + * there is a real-mode segmented pointer pointing to the + * 4K EBDA area at 0x40E. + */ +static inline unsigned int get_bios_ebda(void) +{ + unsigned int address = *(unsigned short *)phys_to_virt(0x40E); + address <<= 4; + return address; /* 0 means none */ +} + +void reserve_ebda_region(void); + +#ifdef CONFIG_X86_CHECK_BIOS_CORRUPTION +/* + * This is obviously not a great place for this, but we want to be + * able to scatter it around anywhere in the kernel. + */ +void check_for_bios_corruption(void); +void start_periodic_check_for_corruption(void); +#else +static inline void check_for_bios_corruption(void) +{ +} + +static inline void start_periodic_check_for_corruption(void) +{ +} +#endif + +#endif /* _ASM_X86_BIOS_EBDA_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/bitops.h b/libdde-linux26/contrib/arch/x86/include/asm/bitops.h new file mode 100644 index 00000000..02b47a60 --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/bitops.h @@ -0,0 +1,465 @@ +#ifndef _ASM_X86_BITOPS_H +#define _ASM_X86_BITOPS_H + +/* + * Copyright 1992, Linus Torvalds. + * + * Note: inlines with more than a single statement should be marked + * __always_inline to avoid problems with older gcc's inlining heuristics. + */ + +#ifndef _LINUX_BITOPS_H +#error only can be included directly +#endif + +#include +#include + +/* + * These have to be done with inline assembly: that way the bit-setting + * is guaranteed to be atomic. All bit operations return 0 if the bit + * was cleared before the operation and != 0 if it was not. + * + * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). + */ + +#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1) +/* Technically wrong, but this avoids compilation errors on some gcc + versions. */ +#define BITOP_ADDR(x) "=m" (*(volatile long *) (x)) +#else +#define BITOP_ADDR(x) "+m" (*(volatile long *) (x)) +#endif + +#define ADDR BITOP_ADDR(addr) + +/* + * We do the locked ops that don't return the old value as + * a mask operation on a byte. + */ +#define IS_IMMEDIATE(nr) (__builtin_constant_p(nr)) +#define CONST_MASK_ADDR(nr, addr) BITOP_ADDR((void *)(addr) + ((nr)>>3)) +#define CONST_MASK(nr) (1 << ((nr) & 7)) + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static __always_inline void +set_bit(unsigned int nr, volatile unsigned long *addr) +{ + if (IS_IMMEDIATE(nr)) { + asm volatile(LOCK_PREFIX "orb %1,%0" + : CONST_MASK_ADDR(nr, addr) + : "iq" ((u8)CONST_MASK(nr)) + : "memory"); + } else { + asm volatile(LOCK_PREFIX "bts %1,%0" + : BITOP_ADDR(addr) : "Ir" (nr) : "memory"); + } +} + +/** + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __set_bit(int nr, volatile unsigned long *addr) +{ + asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory"); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ +static __always_inline void +clear_bit(int nr, volatile unsigned long *addr) +{ + if (IS_IMMEDIATE(nr)) { + asm volatile(LOCK_PREFIX "andb %1,%0" + : CONST_MASK_ADDR(nr, addr) + : "iq" ((u8)~CONST_MASK(nr))); + } else { + asm volatile(LOCK_PREFIX "btr %1,%0" + : BITOP_ADDR(addr) + : "Ir" (nr)); + } +} + +/* + * clear_bit_unlock - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and implies release semantics before the memory + * operation. It can be used for an unlock. + */ +static inline void clear_bit_unlock(unsigned nr, volatile unsigned long *addr) +{ + barrier(); + clear_bit(nr, addr); +} + +static inline void __clear_bit(int nr, volatile unsigned long *addr) +{ + asm volatile("btr %1,%0" : ADDR : "Ir" (nr)); +} + +/* + * __clear_bit_unlock - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * __clear_bit() is non-atomic and implies release semantics before the memory + * operation. It can be used for an unlock if no other CPUs can concurrently + * modify other bits in the word. + * + * No memory barrier is required here, because x86 cannot reorder stores past + * older loads. Same principle as spin_unlock. + */ +static inline void __clear_bit_unlock(unsigned nr, volatile unsigned long *addr) +{ + barrier(); + __clear_bit(nr, addr); +} + +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +/** + * __change_bit - Toggle a bit in memory + * @nr: the bit to change + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __change_bit(int nr, volatile unsigned long *addr) +{ + asm volatile("btc %1,%0" : ADDR : "Ir" (nr)); +} + +/** + * change_bit - Toggle a bit in memory + * @nr: Bit to change + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void change_bit(int nr, volatile unsigned long *addr) +{ + if (IS_IMMEDIATE(nr)) { + asm volatile(LOCK_PREFIX "xorb %1,%0" + : CONST_MASK_ADDR(nr, addr) + : "iq" ((u8)CONST_MASK(nr))); + } else { + asm volatile(LOCK_PREFIX "btc %1,%0" + : BITOP_ADDR(addr) + : "Ir" (nr)); + } +} + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +{ + int oldbit; + + asm volatile(LOCK_PREFIX "bts %2,%1\n\t" + "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); + + return oldbit; +} + +/** + * test_and_set_bit_lock - Set a bit and return its old value for lock + * @nr: Bit to set + * @addr: Address to count from + * + * This is the same as test_and_set_bit on x86. + */ +static __always_inline int +test_and_set_bit_lock(int nr, volatile unsigned long *addr) +{ + return test_and_set_bit(nr, addr); +} + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) +{ + int oldbit; + + asm("bts %2,%1\n\t" + "sbb %0,%0" + : "=r" (oldbit), ADDR + : "Ir" (nr)); + return oldbit; +} + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + int oldbit; + + asm volatile(LOCK_PREFIX "btr %2,%1\n\t" + "sbb %0,%0" + : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); + + return oldbit; +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + int oldbit; + + asm volatile("btr %2,%1\n\t" + "sbb %0,%0" + : "=r" (oldbit), ADDR + : "Ir" (nr)); + return oldbit; +} + +/* WARNING: non atomic and it can be reordered! */ +static inline int __test_and_change_bit(int nr, volatile unsigned long *addr) +{ + int oldbit; + + asm volatile("btc %2,%1\n\t" + "sbb %0,%0" + : "=r" (oldbit), ADDR + : "Ir" (nr) : "memory"); + + return oldbit; +} + +/** + * test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +{ + int oldbit; + + asm volatile(LOCK_PREFIX "btc %2,%1\n\t" + "sbb %0,%0" + : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); + + return oldbit; +} + +static __always_inline int constant_test_bit(unsigned int nr, const volatile unsigned long *addr) +{ + return ((1UL << (nr % BITS_PER_LONG)) & + (((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0; +} + +static inline int variable_test_bit(int nr, volatile const unsigned long *addr) +{ + int oldbit; + + asm volatile("bt %2,%1\n\t" + "sbb %0,%0" + : "=r" (oldbit) + : "m" (*(unsigned long *)addr), "Ir" (nr)); + + return oldbit; +} + +#if 0 /* Fool kernel-doc since it doesn't do macros yet */ +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static int test_bit(int nr, const volatile unsigned long *addr); +#endif + +#define test_bit(nr, addr) \ + (__builtin_constant_p((nr)) \ + ? constant_test_bit((nr), (addr)) \ + : variable_test_bit((nr), (addr))) + +/** + * __ffs - find first set bit in word + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static inline unsigned long __ffs(unsigned long word) +{ + asm("bsf %1,%0" + : "=r" (word) + : "rm" (word)); + return word; +} + +/** + * ffz - find first zero bit in word + * @word: The word to search + * + * Undefined if no zero exists, so code should check against ~0UL first. + */ +static inline unsigned long ffz(unsigned long word) +{ + asm("bsf %1,%0" + : "=r" (word) + : "r" (~word)); + return word; +} + +/* + * __fls: find last set bit in word + * @word: The word to search + * + * Undefined if no set bit exists, so code should check against 0 first. + */ +static inline unsigned long __fls(unsigned long word) +{ + asm("bsr %1,%0" + : "=r" (word) + : "rm" (word)); + return word; +} + +#ifdef __KERNEL__ +/** + * ffs - find first set bit in word + * @x: the word to search + * + * This is defined the same way as the libc and compiler builtin ffs + * routines, therefore differs in spirit from the other bitops. + * + * ffs(value) returns 0 if value is 0 or the position of the first + * set bit if value is nonzero. The first (least significant) bit + * is at position 1. + */ +static inline int ffs(int x) +{ + int r; +#ifdef CONFIG_X86_CMOV + asm("bsfl %1,%0\n\t" + "cmovzl %2,%0" + : "=r" (r) : "rm" (x), "r" (-1)); +#else + asm("bsfl %1,%0\n\t" + "jnz 1f\n\t" + "movl $-1,%0\n" + "1:" : "=r" (r) : "rm" (x)); +#endif + return r + 1; +} + +/** + * fls - find last set bit in word + * @x: the word to search + * + * This is defined in a similar way as the libc and compiler builtin + * ffs, but returns the position of the most significant set bit. + * + * fls(value) returns 0 if value is 0 or the position of the last + * set bit if value is nonzero. The last (most significant) bit is + * at position 32. + */ +static inline int fls(int x) +{ + int r; +#ifdef CONFIG_X86_CMOV + asm("bsrl %1,%0\n\t" + "cmovzl %2,%0" + : "=&r" (r) : "rm" (x), "rm" (-1)); +#else + asm("bsrl %1,%0\n\t" + "jnz 1f\n\t" + "movl $-1,%0\n" + "1:" : "=r" (r) : "rm" (x)); +#endif + return r + 1; +} +#endif /* __KERNEL__ */ + +#undef ADDR + +#ifdef __KERNEL__ + +#include + +#define ARCH_HAS_FAST_MULTIPLIER 1 + +#include + +#endif /* __KERNEL__ */ + +#include + +#ifdef __KERNEL__ + +#include + +#define ext2_set_bit_atomic(lock, nr, addr) \ + test_and_set_bit((nr), (unsigned long *)(addr)) +#define ext2_clear_bit_atomic(lock, nr, addr) \ + test_and_clear_bit((nr), (unsigned long *)(addr)) + +#include + +#endif /* __KERNEL__ */ +#endif /* _ASM_X86_BITOPS_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/boot.h b/libdde-linux26/contrib/arch/x86/include/asm/boot.h new file mode 100644 index 00000000..dd61616c --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/boot.h @@ -0,0 +1,26 @@ +#ifndef _ASM_X86_BOOT_H +#define _ASM_X86_BOOT_H + +/* Don't touch these, unless you really know what you're doing. */ +#define DEF_SYSSEG 0x1000 +#define DEF_SYSSIZE 0x7F00 + +/* Internal svga startup constants */ +#define NORMAL_VGA 0xffff /* 80x25 mode */ +#define EXTENDED_VGA 0xfffe /* 80x50 mode */ +#define ASK_VGA 0xfffd /* ask for it at bootup */ + +/* Physical address where kernel should be loaded. */ +#define LOAD_PHYSICAL_ADDR ((CONFIG_PHYSICAL_START \ + + (CONFIG_PHYSICAL_ALIGN - 1)) \ + & ~(CONFIG_PHYSICAL_ALIGN - 1)) + +#ifdef CONFIG_X86_64 +#define BOOT_HEAP_SIZE 0x7000 +#define BOOT_STACK_SIZE 0x4000 +#else +#define BOOT_HEAP_SIZE 0x4000 +#define BOOT_STACK_SIZE 0x1000 +#endif + +#endif /* _ASM_X86_BOOT_H */ diff --git a/libdde-linux26/contrib/arch/x86/include/asm/bootparam.h b/libdde-linux26/contrib/arch/x86/include/asm/bootparam.h new file mode 100644 index 00000000..433adaeb --- /dev/null +++ b/libdde-linux26/contrib/arch/x86/include/asm/bootparam.h @@ -0,0 +1,111 @@ +#ifndef _ASM_X86_BOOTPARAM_H +#define _ASM_X86_BOOTPARAM_H + +#include +#include +#include +#include +#include +#include +#include