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/*
* Copyright (c) 1995-1994 The University of Utah and
* the Computer Systems Laboratory at the University of Utah (CSL).
* All rights reserved.
*
* Permission to use, copy, modify and distribute this software is hereby
* granted provided that (1) source code retains these copyright, permission,
* and disclaimer notices, and (2) redistributions including binaries
* reproduce the notices in supporting documentation, and (3) all advertising
* materials mentioning features or use of this software display the following
* acknowledgement: ``This product includes software developed by the
* Computer Systems Laboratory at the University of Utah.''
*
* THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
* IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
* ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* CSL requests users of this software to return to csl-dist@cs.utah.edu any
* improvements that they make and grant CSL redistribution rights.
*
* Author: Bryan Ford, University of Utah CSL
*/
#include <mach/machine/seg.h>
#include <mach/machine/proc_reg.h>
#include "vm_param.h"
#include "cpu.h"
struct idt_init_entry
{
unsigned entrypoint;
unsigned short vector;
unsigned short type;
};
extern struct idt_init_entry idt_inittab[];
void cpu_idt_init(struct cpu *cpu)
{
struct idt_init_entry *iie = idt_inittab;
/* Initialize the trap/interrupt vectors from the idt_inittab. */
while (iie->entrypoint)
{
fill_idt_gate(cpu, iie->vector, iie->entrypoint,
KERNEL_CS, iie->type);
iie++;
}
}
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