From 5c1f862c2ceccc3326d444879bf85d77b34ee2ea Mon Sep 17 00:00:00 2001 From: Samuel Thibault Date: Fri, 6 Jul 2007 16:33:48 +0000 Subject: 2007-07-04 Samuel Thibault * i386/intel/pmap.c (pmap_enter): Use INTEL_PTE_NCACHE|INTEL_PTE_WTHRU when cpu >= 486 and physical address is after memory end. --- ChangeLog | 5 +++++ i386/intel/pmap.c | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/ChangeLog b/ChangeLog index 06ad58f..2aea8b7 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,8 @@ +2007-07-04 Samuel Thibault + + * i386/intel/pmap.c (pmap_enter): Use INTEL_PTE_NCACHE|INTEL_PTE_WTHRU + when cpu >= 486 and physical address is after memory end. + 2007-06-23 Samuel Thibault * i386/i386/trap.c (user_trap): Read faulting linear address before diff --git a/i386/intel/pmap.c b/i386/intel/pmap.c index 1043daa..7746c61 100644 --- a/i386/intel/pmap.c +++ b/i386/intel/pmap.c @@ -1506,6 +1506,9 @@ Retry: template |= INTEL_PTE_USER; if (prot & VM_PROT_WRITE) template |= INTEL_PTE_WRITE; + if (machine_slot[cpu_number()].cpu_type >= CPU_TYPE_I486 + && pa >= phys_last_addr) + template |= INTEL_PTE_NCACHE|INTEL_PTE_WTHRU; if (wired) template |= INTEL_PTE_WIRED; PMAP_UPDATE_TLBS(pmap, v, v + PAGE_SIZE); @@ -1615,6 +1618,9 @@ Retry: template |= INTEL_PTE_USER; if (prot & VM_PROT_WRITE) template |= INTEL_PTE_WRITE; + if (machine_slot[cpu_number()].cpu_type >= CPU_TYPE_I486 + && pa >= phys_last_addr) + template |= INTEL_PTE_NCACHE|INTEL_PTE_WTHRU; if (wired) template |= INTEL_PTE_WIRED; i = ptes_per_vm_page; -- cgit v1.2.3